OV - exec - Function main

	Function: main	Module: exec	Source: main.c:50-192 [...]	Coverage (incl. loops): 0.03% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c: 50 - 192

--------------------------------------------------------------------------------

50: {

[...]

57:   double t3, elapsed = 0.0, validation, final, t1, t2;

[...]

63:   long NN = N;

[...]

73:       printf( "count is set %d\n", count );

74:       printf( "Total MPI ranks %d\n", nprocs );

75:   }

76:

77:   if (argc == 2 && strncmp(argv[1], "-s", 2) == 0)

78:       NN = 15000;

79:

80:   printf( "N is set %ld\n", NN );

81:

82: #pragma omp parallel

[...]

97:   for ( n = 400; n < NN; n = n + 20 )

[...]

103:       dx1 = 1.0f/(float)n;

104:       dy1 = 2.0f/(float)n;

105:       dz1 = 3.0f/(float)n;

106:       xx[0] = 0.f;

107:       yy[0] = 0.f;

108:       zz[0] = 0.f;

109:       mass[0] = 2.f;

110:

111:       for ( i = 1; i < n; i++ )

112:       {

113:           xx[i] = xx[i-1] + dx1;

114:           yy[i] = yy[i-1] + dy1;

115:           zz[i] = zz[i-1] + dz1;

116:           mass[i] = (float)i * 0.01f + xx[i];

117:       }

118:

119:       for ( i = 0; i < n; i++ )

120:       {

121:           vx1[i] = 0.f;

122:           vy1[i] = 0.f;

123:           vz1[i] = 0.f;

[...]

136:       t1 = mysecond();

137: #endif

138:

139:     #pragma omp parallel for private( dx1, dy1, dz1 )

[...]

152:       t2 = mysecond();

[...]

166:       t3 = (t2 - t1) * 1e6;

167: #endif

168:

169:       elapsed = elapsed + t3;

[...]

185:       printf( "\nKernel elapsed time, s: %18.8lf\n", elapsed*1e-6 );

[...]

192: }

0x4010b0 PUSH	%RBP

0x4010b1 XOR	%EAX,%EAX

0x4010b3 MOV	%RSP,%RBP

0x4010b6 PUSH	%R15

0x4010b8 PUSH	%R14

0x4010ba PUSH	%R13

0x4010bc PUSH	%R12

0x4010be PUSH	%RBX

0x4010bf MOV	%RSI,%R12

0x4010c2 MOV	%EDI,%EBX

0x4010c4 SUB	$0x38,%RSP

0x4010c8 MOV	$0xbb8,%ESI

0x4010cd MOV	$0x40201f,%EDI

0x4010d2 MOV	$0x186a0,%R13D

0x4010d8 CALL	401030 <printf@plt>

0x4010dd MOV	$0x1,%ESI

0x4010e2 MOV	$0x402030,%EDI

0x4010e7 XOR	%EAX,%EAX

0x4010e9 CALL	401030 <printf@plt>

0x4010ee CMP	$0x2,%EBX

0x4010f1 JNE	40111b

0x4010f3 MOV	0x8(%R12),%RDI

0x4010f8 MOV	$0x2,%EDX

0x4010fd MOV	$0x402044,%ESI

0x401102 CALL	401070 <strncmp@plt>

0x401107 CMP	$0x1,%EAX

0x40110a SBB	%R13,%R13

0x40110d AND	$-0x14c08,%R13

0x401114 ADD	$0x186a0,%R13

0x40111b MOV	%R13,%RSI

0x40111e MOV	$0x402047,%EDI

0x401123 XOR	%EAX,%EAX

0x401125 CALL	401030 <printf@plt>

0x40112a XOR	%EDX,%EDX

0x40112c XOR	%ECX,%ECX

0x40112e LEA	-0x50(%RBP),%RSI

0x401132 MOV	$0x4018e0,%EDI

0x401137 MOVL	$0,-0x50(%RBP)

0x40113e CALL	401090 <GOMP_parallel@plt>

0x401143 VMOVSS	0xf3d(%RIP),%XMM7

0x40114b MOV	0xf3e(%RIP),%R14

0x401152 MOV	$0x190,%EDX

0x401157 VXORPD	%XMM8,%XMM8,%XMM8

0x40115c VXORPS	%XMM5,%XMM5,%XMM5

(1) 0x401160 VMOVSS	0xf14(%RIP),%XMM6

(1) 0x401168 VMOVSS	0xf10(%RIP),%XMM0

(1) 0x401170 VMOVSS	0xf0c(%RIP),%XMM1

(1) 0x401178 LEA	-0x1(%RDX),%RAX

(1) 0x40117c AND	$0x3,%EAX

(1) 0x40117f VCVTSI2SS	%EDX,%XMM5,%XMM3

(1) 0x401183 MOV	%EDX,%R12D

(1) 0x401186 MOV	$0x1,%EBX

(1) 0x40118b VXORPS	%XMM13,%XMM13,%XMM13

(1) 0x401190 MOVL	$0,0x189906(%RIP)

(1) 0x40119a MOVL	$0,0x1eb37c(%RIP)

(1) 0x4011a4 MOVL	$0,0x24cdf2(%RIP)

(1) 0x4011ae VMOVAPS	%XMM13,%XMM2

(1) 0x4011b2 VMOVAPS	%XMM13,%XMM14

(1) 0x4011b7 MOVL	$0x40000000,0x127e5f(%RIP)

(1) 0x4011c1 VDIVSS	%XMM3,%XMM6,%XMM9

(1) 0x4011c5 VDIVSS	%XMM3,%XMM0,%XMM10

(1) 0x4011c9 VDIVSS	%XMM3,%XMM1,%XMM11

(1) 0x4011cd JE	4012a7

(1) 0x4011d3 CMP	$0x1,%RAX

(1) 0x4011d7 JE	40125f

(1) 0x4011dd CMP	$0x2,%RAX

(1) 0x4011e1 JE	401220

(1) 0x4011e3 VADDSS	%XMM9,%XMM13,%XMM13

(1) 0x4011e8 VCVTSI2SS	%EBX,%XMM5,%XMM4

(1) 0x4011ec VADDSS	%XMM10,%XMM2,%XMM2

(1) 0x4011f1 MOV	$0x2,%EBX

(1) 0x4011f6 VADDSS	%XMM11,%XMM14,%XMM14

(1) 0x4011fb VFMADD132SS	%XMM7,%XMM13,%XMM4

(1) 0x401200 VMOVSS	%XMM13,0x18989c(%RIP)

(1) 0x401208 VMOVSS	%XMM2,0x1eb314(%RIP)

(1) 0x401210 VMOVSS	%XMM14,0x24cd8c(%RIP)

(1) 0x401218 VMOVSS	%XMM4,0x127e04(%RIP)

(1) 0x401220 VADDSS	%XMM9,%XMM13,%XMM13

(1) 0x401225 VCVTSI2SS	%EBX,%XMM5,%XMM12

(1) 0x401229 VADDSS	%XMM10,%XMM2,%XMM2

(1) 0x40122e VADDSS	%XMM11,%XMM14,%XMM14

(1) 0x401233 VFMADD132SS	%XMM7,%XMM13,%XMM12

(1) 0x401238 VMOVSS	%XMM13,0x58aaa0(,%RBX,4)

(1) 0x401241 VMOVSS	%XMM2,0x5ec520(,%RBX,4)

(1) 0x40124a VMOVSS	%XMM14,0x64dfa0(,%RBX,4)

(1) 0x401253 VMOVSS	%XMM12,0x529020(,%RBX,4)

(1) 0x40125c INC	%RBX

(1) 0x40125f VADDSS	%XMM9,%XMM13,%XMM13

(1) 0x401264 VCVTSI2SS	%EBX,%XMM5,%XMM15

(1) 0x401268 VADDSS	%XMM10,%XMM2,%XMM2

(1) 0x40126d VADDSS	%XMM11,%XMM14,%XMM14

(1) 0x401272 VFMADD132SS	%XMM7,%XMM13,%XMM15

(1) 0x401277 VMOVSS	%XMM13,0x58aaa0(,%RBX,4)

(1) 0x401280 VMOVSS	%XMM2,0x5ec520(,%RBX,4)

(1) 0x401289 VMOVSS	%XMM14,0x64dfa0(,%RBX,4)

(1) 0x401292 VMOVSS	%XMM15,0x529020(,%RBX,4)

(1) 0x40129b INC	%RBX

(1) 0x40129e CMP	%RDX,%RBX

(1) 0x4012a1 JE	4013b0

  (0) 0x4012a7 VADDSS	%XMM9,%XMM13,%XMM3

  (0) 0x4012ac VADDSS	%XMM10,%XMM2,%XMM6

  (0) 0x4012b1 LEA	0x1(%RBX),%RCX

  (0) 0x4012b5 VCVTSI2SS	%EBX,%XMM5,%XMM0

  (0) 0x4012b9 VADDSS	%XMM11,%XMM14,%XMM1

  (0) 0x4012be LEA	0x2(%RBX),%RSI

  (0) 0x4012c2 LEA	0x3(%RBX),%RDI

  (0) 0x4012c6 VCVTSI2SS	%ECX,%XMM5,%XMM4

  (0) 0x4012ca VADDSS	%XMM9,%XMM3,%XMM12

  (0) 0x4012cf VADDSS	%XMM10,%XMM6,%XMM13

  (0) 0x4012d4 VMOVSS	%XMM6,0x5ec520(,%RBX,4)

  (0) 0x4012dd VFMADD132SS	%XMM7,%XMM3,%XMM0

  (0) 0x4012e2 VADDSS	%XMM11,%XMM1,%XMM14

  (0) 0x4012e7 VMOVSS	%XMM3,0x58aaa0(,%RBX,4)

  (0) 0x4012f0 VCVTSI2SS	%ESI,%XMM5,%XMM6

  (0) 0x4012f4 VMOVSS	%XMM1,0x64dfa0(,%RBX,4)

  (0) 0x4012fd VCVTSI2SS	%EDI,%XMM5,%XMM1

  (0) 0x401301 VADDSS	%XMM9,%XMM12,%XMM15

  (0) 0x401306 VADDSS	%XMM10,%XMM13,%XMM2

  (0) 0x40130b VMOVSS	%XMM13,0x5ec520(,%RCX,4)

  (0) 0x401314 VFMADD132SS	%XMM7,%XMM12,%XMM4

  (0) 0x401319 VADDSS	%XMM11,%XMM14,%XMM3

  (0) 0x40131e VMOVSS	%XMM14,0x64dfa0(,%RCX,4)

  (0) 0x401327 VMOVSS	%XMM0,0x529020(,%RBX,4)

  (0) 0x401330 ADD	$0x4,%RBX

  (0) 0x401334 VADDSS	%XMM9,%XMM15,%XMM13

  (0) 0x401339 VFMADD132SS	%XMM7,%XMM15,%XMM6

  (0) 0x40133e VMOVSS	%XMM2,0x5ec520(,%RSI,4)

  (0) 0x401347 VADDSS	%XMM10,%XMM2,%XMM2

  (0) 0x40134c VADDSS	%XMM11,%XMM3,%XMM14

  (0) 0x401351 VMOVSS	%XMM12,0x58aaa0(,%RCX,4)

  (0) 0x40135a VMOVSS	%XMM4,0x529020(,%RCX,4)

  (0) 0x401363 VFMADD132SS	%XMM7,%XMM13,%XMM1

  (0) 0x401368 VMOVSS	%XMM15,0x58aaa0(,%RSI,4)

  (0) 0x401371 VMOVSS	%XMM3,0x64dfa0(,%RSI,4)

  (0) 0x40137a VMOVSS	%XMM6,0x529020(,%RSI,4)

  (0) 0x401383 VMOVSS	%XMM13,0x58aaa0(,%RDI,4)

  (0) 0x40138c VMOVSS	%XMM2,0x5ec520(,%RDI,4)

  (0) 0x401395 VMOVSS	%XMM14,0x64dfa0(,%RDI,4)

  (0) 0x40139e VMOVSS	%XMM1,0x529020(,%RDI,4)

  (0) 0x4013a7 CMP	%RDX,%RBX

  (0) 0x4013aa JNE	4012a7

(1) 0x4013b0 LEA	(,%RBX,4),%R15

(1) 0x4013b8 XOR	%ESI,%ESI

(1) 0x4013ba MOV	$0x4c75a0,%EDI

(1) 0x4013bf VMOVSD	%XMM8,-0x60(%RBP)

(1) 0x4013c4 MOV	%R15,%RDX

(1) 0x4013c7 CALL	401040 <memset@plt>

(1) 0x4013cc XOR	%ESI,%ESI

(1) 0x4013ce MOV	%R15,%RDX

(1) 0x4013d1 MOV	$0x465b20,%EDI

(1) 0x4013d6 CALL	401040 <memset@plt>

(1) 0x4013db XOR	%ESI,%ESI

(1) 0x4013dd MOV	%R15,%RDX

(1) 0x4013e0 MOV	$0x4040a0,%EDI

(1) 0x4013e5 CALL	401040 <memset@plt>

(1) 0x4013ea XOR	%EAX,%EAX

(1) 0x4013ec CALL	401920 <mysecond>

(1) 0x4013f1 XOR	%EDX,%EDX

(1) 0x4013f3 XOR	%ECX,%ECX

(1) 0x4013f5 LEA	-0x50(%RBP),%RSI

(1) 0x4013f9 MOV	$0x401570,%EDI

(1) 0x4013fe VMOVSD	%XMM0,-0x58(%RBP)

(1) 0x401403 MOVL	$0xbb8,-0x40(%RBP)

(1) 0x40140a MOV	%R12D,-0x44(%RBP)

(1) 0x40140e MOVL	$0x3e6b851f,-0x48(%RBP)

(1) 0x401415 MOV	%R14,-0x50(%RBP)

(1) 0x401419 CALL	401090 <GOMP_parallel@plt>

(1) 0x40141e XOR	%EAX,%EAX

(1) 0x401420 CALL	401920 <mysecond>

(1) 0x401425 LEA	0x14(%RBX),%RDX

(1) 0x401429 VSUBSD	-0x58(%RBP),%XMM0,%XMM5

(1) 0x40142e VMOVSD	-0x60(%RBP),%XMM8

(1) 0x401433 CMP	%RDX,%R13

(1) 0x401436 VFMADD231SD	0xc59(%RIP),%XMM5,%XMM8

(1) 0x40143f VMOVSS	0xc41(%RIP),%XMM7

(1) 0x401447 VXORPS	%XMM5,%XMM5,%XMM5

(1) 0x40144b JG	401160

0x401451 MOV	$0x402058,%EDI

0x401456 MOV	$0x1,%EAX

0x40145b VMULSD	0xc3d(%RIP),%XMM8,%XMM0

0x401463 CALL	401030 <printf@plt>

0x401468 ADD	$0x38,%RSP

0x40146c XOR	%EAX,%EAX

0x40146e POP	%RBX

0x40146f POP	%R12

0x401471 POP	%R13

0x401473 POP	%R14

0x401475 POP	%R15

0x401477 POP	%RBP

0x401478 RET

0x401479 NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○100.00	__libc_start_call_main		libc.so.6

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_no_fastmath

Source file and lines	main.c:50-192
Module	exec

The function is defined in /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:50,57,63,73-82,97,103-123,136-139,152,166-169,185,192.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.50 to 1.17 cycles (9.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 10.50 to 0.72 cycles (14.50x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

GOMP_parallel@plt: 1 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:82
printf@plt: 4 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:73
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:74
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:80
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:185
strncmp@plt: 1 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:77

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 28 bytes (3 double precision FP elements). The binary function is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	58
nb uops	63
loop length	223
used x86 registers	12
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.50 cycles
front end	10.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.00	6.00	6.00	6.00	4.00	3.67	3.67	3.67	0.50	0.50	0.00	0.00	0.00	0.00
cycles	6.00	6.00	6.00	6.00	4.00	3.67	3.67	3.67	0.50	0.50	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.50
Dispatch	6.00
Overall L1	10.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	7%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Vector efficiency ratios

INT

all	7%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	17%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	9%
load	10%
store	6%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.50 cycles. At this rate:

2% of peak load performance is reached (2.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.38 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 10.50 to 6.00 cycles (1.75x speedup).

ASM code

In the binary file, the address of the function is: 4010b0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EDI,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB $0x38,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV $0xbb8,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x40201f,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x186a0,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
CALL 401030 <printf@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
MOV $0x1,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x402030,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CALL 401030 <printf@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
CMP $0x2,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JNE 40111b <main+0x6b>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
MOV 0x8(%R12),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	scal (12.5%)
MOV $0x2,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x402044,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
CALL 401070 <strncmp@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
CMP $0x1,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
SBB %R13,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
AND $-0x14c08,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD $0x186a0,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV %R13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV $0x402047,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CALL 401030 <printf@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
LEA -0x50(%RBP),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV $0x4018e0,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOVL $0,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
CALL 401090 <GOMP_parallel@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
VMOVSS 0xf3d(%RIP),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (6.3%)
MOV 0xf3e(%RIP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	scal (12.5%)
MOV $0x190,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
VXORPD %XMM8,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV $0x402058,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x1,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
VMULSD 0xc3d(%RIP),%XMM8,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	3	0.50	scal (12.5%)
CALL 401030 <printf@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
ADD $0x38,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_no_fastmath

Source file and lines	main.c:50-192
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.50 to 1.17 cycles (9.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

GOMP_parallel@plt: 1 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:82
printf@plt: 4 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:73
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:74
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:80
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:185
strncmp@plt: 1 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:77

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 28 bytes (3 double precision FP elements). The binary function is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	58
nb uops	63
loop length	223
used x86 registers	12
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.50 cycles
front end	10.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.00	6.00	6.00	6.00	4.00	3.67	3.67	3.67	0.50	0.50	0.00	0.00	0.00	0.00
cycles	6.00	6.00	6.00	6.00	4.00	3.67	3.67	3.67	0.50	0.50	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.50
Dispatch	6.00
Overall L1	10.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	7%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Vector efficiency ratios

INT

all	7%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	17%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	9%
load	10%
store	6%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.50 cycles. At this rate:

2% of peak load performance is reached (2.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.38 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4010b0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EDI,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB $0x38,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV $0xbb8,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x40201f,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x186a0,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
CALL 401030 <printf@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
MOV $0x1,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x402030,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CALL 401030 <printf@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
CMP $0x2,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JNE 40111b <main+0x6b>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
MOV 0x8(%R12),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	scal (12.5%)
MOV $0x2,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x402044,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
CALL 401070 <strncmp@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
CMP $0x1,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
SBB %R13,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
AND $-0x14c08,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD $0x186a0,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV %R13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV $0x402047,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CALL 401030 <printf@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
LEA -0x50(%RBP),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV $0x4018e0,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOVL $0,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
CALL 401090 <GOMP_parallel@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
VMOVSS 0xf3d(%RIP),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (6.3%)
MOV 0xf3e(%RIP),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	scal (12.5%)
MOV $0x190,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
VXORPD %XMM8,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV $0x402058,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x1,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
VMULSD 0xc3d(%RIP),%XMM8,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	3	0.50	scal (12.5%)
CALL 401030 <printf@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
ADD $0x38,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main–	0.03	0.03
▼Loop 1 - main.c:97-169 - exec–	0.00	0.00
○Loop 0 - main.c:111-116 - exec	0.03	5.27

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code