OV - exec - Function Step10

	Function: Step10_orig	Module: exec	Source: Step10_orig.c:10-41 [...]	Coverage (incl. loops): 14.63% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 10 - 41

--------------------------------------------------------------------------------

10: {

[...]

17:     xi = 0.; yi = 0.; zi = 0.;

18:

19:     for ( j = 0; j < count1; j++ )

20:     {

21:         dxc = xx1[j] - xxi;

22:         dyc = yy1[j] - yyi;

23:         dzc = zz1[j] - zzi;

24:

25:         r2 = dxc * dxc + dyc * dyc + dzc * dzc;

26:

27:         m = ( r2 < fsrrmax2 ) ? mass1[j] : 0.0f;

28:

29:         f =  pow( r2 + mp_rsm2, -1.5 ) - ( ma0 + r2*(ma1 + r2*(ma2 + r2*(ma3 + r2*(ma4 + r2*ma5)))));

30:

31:         f = ( r2 > 0.0f ) ? m * f : 0.0f;

32:

33:         xi = xi + f * dxc;

34:         yi = yi + f * dyc;

35:         zi = zi + f * dzc;

36:     }

37:

38:     *dxi = xi;

39:     *dyi = yi;

40:     *dzi = zi;

41: }

0x401980 PUSH	%RBP

0x401981 MOV	%RSP,%RBP

0x401984 PUSH	%R15

0x401986 PUSH	%R14

0x401988 PUSH	%R13

0x40198a PUSH	%R12

0x40198c PUSH	%RBX

0x40198d MOVSXD	%EDI,%RBX

0x401990 SUB	$0x58,%RSP

0x401994 VMOVSS	%XMM0,-0x54(%RBP)

0x401999 MOV	%R8,-0x70(%RBP)

0x40199d MOV	%R9,-0x78(%RBP)

0x4019a1 VMOVSS	%XMM1,-0x58(%RBP)

0x4019a6 VMOVSS	%XMM2,-0x5c(%RBP)

0x4019ab VMOVSS	%XMM3,-0x60(%RBP)

0x4019b0 VMOVSS	%XMM4,-0x64(%RBP)

0x4019b5 TEST	%EBX,%EBX

0x4019b7 JLE	401b70

0x4019bd VXORPS	%XMM6,%XMM6,%XMM6

0x4019c1 MOV	%RSI,%R12

0x4019c4 MOV	%RDX,%R13

0x4019c7 MOV	%RCX,%R14

0x4019ca SAL	$0x2,%RBX

0x4019ce VMOVAPS	%XMM6,%XMM7

0x4019d2 VMOVAPS	%XMM6,%XMM8

0x4019d6 XOR	%R15D,%R15D

0x4019d9 NOPL	(%RAX)

(3) 0x4019e0 VMOVSS	(%R13,%R15,1),%XMM4

(3) 0x4019e7 VSUBSS	-0x58(%RBP),%XMM4,%XMM10

(3) 0x4019ec VMOVSS	(%R12,%R15,1),%XMM5

(3) 0x4019f2 VSUBSS	-0x54(%RBP),%XMM5,%XMM9

(3) 0x4019f7 VMOVSS	(%R14,%R15,1),%XMM3

(3) 0x4019fd VSUBSS	-0x5c(%RBP),%XMM3,%XMM11

(3) 0x401a02 VMOVSS	-0x60(%RBP),%XMM1

(3) 0x401a07 VMULSS	%XMM10,%XMM10,%XMM2

(3) 0x401a0c VFMADD231SS	%XMM9,%XMM9,%XMM2

(3) 0x401a11 VFMADD231SS	%XMM11,%XMM11,%XMM2

(3) 0x401a16 VCOMISS	%XMM2,%XMM1

(3) 0x401a1a JBE	401b30

(3) 0x401a20 MOV	-0x70(%RBP),%RAX

(3) 0x401a24 VMOVSS	(%RAX,%R15,1),%XMM0

(3) 0x401a2a VMOVSS	%XMM0,-0x50(%RBP)

(3) 0x401a2f VADDSS	-0x64(%RBP),%XMM2,%XMM12

(3) 0x401a34 MOV	0x66d(%RIP),%RDX

(3) 0x401a3b VMOVSS	%XMM10,-0x48(%RBP)

(3) 0x401a40 VMOVSS	%XMM9,-0x44(%RBP)

(3) 0x401a45 VMOVSS	%XMM7,-0x40(%RBP)

(3) 0x401a4a VMOVSS	%XMM8,-0x3c(%RBP)

(3) 0x401a4f VMOVSS	%XMM6,-0x38(%RBP)

(3) 0x401a54 VMOVQ	%RDX,%XMM1

(3) 0x401a59 VMOVSS	%XMM11,-0x4c(%RBP)

(3) 0x401a5e VMOVSS	%XMM2,-0x34(%RBP)

(3) 0x401a63 VCVTSS2SD	%XMM12,%XMM12,%XMM0

(3) 0x401a68 CALL	4010a0 <pow@plt>

(3) 0x401a6d VMOVSS	-0x34(%RBP),%XMM14

(3) 0x401a72 VXORPS	%XMM13,%XMM13,%XMM13

(3) 0x401a77 VMOVSS	-0x38(%RBP),%XMM6

(3) 0x401a7c VMOVSS	-0x3c(%RBP),%XMM8

(3) 0x401a81 VMOVSS	-0x40(%RBP),%XMM7

(3) 0x401a86 VMOVSS	-0x44(%RBP),%XMM15

(3) 0x401a8b VMOVSS	-0x48(%RBP),%XMM9

(3) 0x401a90 VMOVSS	-0x4c(%RBP),%XMM10

(3) 0x401a95 VCOMISS	%XMM13,%XMM14

(3) 0x401a9a JBE	401b40

(3) 0x401aa0 VMOVSS	0x608(%RIP),%XMM3

(3) 0x401aa8 VFMADD213SS	0x603(%RIP),%XMM14,%XMM3

(3) 0x401ab1 VFMADD213SS	0x5fe(%RIP),%XMM14,%XMM3

(3) 0x401aba VFMADD213SS	0x5f9(%RIP),%XMM14,%XMM3

(3) 0x401ac3 VFMADD213SS	0x5f4(%RIP),%XMM14,%XMM3

(3) 0x401acc VFMADD213SS	0x5ef(%RIP),%XMM14,%XMM3

(3) 0x401ad5 VCVTSS2SD	%XMM3,%XMM3,%XMM11

(3) 0x401ad9 VSUBSD	%XMM11,%XMM0,%XMM2

(3) 0x401ade VCVTSD2SS	%XMM2,%XMM2,%XMM1

(3) 0x401ae2 VMULSS	-0x50(%RBP),%XMM1,%XMM0

(3) 0x401ae7 ADD	$0x4,%R15

(3) 0x401aeb VFMADD231SS	%XMM0,%XMM15,%XMM8

(3) 0x401af0 VFMADD231SS	%XMM0,%XMM9,%XMM7

(3) 0x401af5 VFMADD231SS	%XMM0,%XMM10,%XMM6

(3) 0x401afa CMP	%RBX,%R15

(3) 0x401afd JNE	4019e0

0x401b03 MOV	-0x78(%RBP),%RCX

0x401b07 MOV	0x10(%RBP),%RSI

0x401b0b MOV	0x18(%RBP),%RDI

0x401b0f VMOVSS	%XMM8,(%RCX)

0x401b13 VMOVSS	%XMM7,(%RSI)

0x401b17 VMOVSS	%XMM6,(%RDI)

0x401b1b ADD	$0x58,%RSP

0x401b1f POP	%RBX

0x401b20 POP	%R12

0x401b22 POP	%R13

0x401b24 POP	%R14

0x401b26 POP	%R15

0x401b28 POP	%RBP

0x401b29 RET

0x401b2a NOPW	(%RAX,%RAX,1)

(3) 0x401b30 MOVL	$0,-0x50(%RBP)

(3) 0x401b37 JMP	401a2f

0x401b3c NOPL	(%RAX)

(3) 0x401b40 VXORPS	%XMM5,%XMM5,%XMM5

(3) 0x401b44 ADD	$0x4,%R15

(3) 0x401b48 VFMADD231SS	%XMM5,%XMM15,%XMM8

(3) 0x401b4d VFMADD231SS	%XMM5,%XMM9,%XMM7

(3) 0x401b52 VFMADD231SS	%XMM5,%XMM10,%XMM6

(3) 0x401b57 CMP	%R15,%RBX

(3) 0x401b5a JNE	4019e0

0x401b60 JMP	401b03

0x401b62 NOPW	%CS:(%RAX,%RAX,1)

0x401b6d NOPL	(%RAX)

0x401b70 VXORPS	%XMM6,%XMM6,%XMM6

0x401b74 VMOVAPS	%XMM6,%XMM7

0x401b78 VMOVAPS	%XMM6,%XMM8

0x401b7c JMP	401b03

Coverage (%)	Name	Source Location	Module
►44.69+	main._omp_fn.1	main.c:144	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►44.57+	main._omp_fn.1	main.c:142	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►6.38+	main._omp_fn.1	main.c:144	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►3.85+	main._omp_fn.1	main.c:144	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_no_fastmath

Source file and lines	Step10_orig.c:10-41
Module	exec

The function is defined in /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:10,17-41.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.50 to 4.00 cycles (1.87x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 7.50 to 0.50 cycles (15.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	50
nb uops	45
loop length	175
used x86 registers	14
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.50 cycles
front end	7.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.00	1.75	1.75	1.50	2.00	4.33	4.33	4.33	0.00	0.00	0.00	0.00	4.00	4.00
cycles	2.00	1.75	1.75	1.50	2.00	4.33	4.33	4.33	0.00	0.00	0.00	0.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.50
Dispatch	4.33
Overall L1	7.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	42%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	26%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	46%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.50 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (6.40 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.50 to 4.33 cycles (1.73x speedup).

ASM code

In the binary file, the address of the function is: 401980

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVSXD %EDI,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB $0x58,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
VMOVSS %XMM0,-0x54(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (6.3%)
MOV %R8,-0x70(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x78(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (12.5%)
VMOVSS %XMM1,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM2,-0x5c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM3,-0x60(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM4,-0x64(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (6.3%)
TEST %EBX,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JLE 401b70 <Step10_orig+0x1f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
VXORPS %XMM6,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x2,%RBX	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVAPS %XMM6,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPS %XMM6,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x78(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	N/A
MOV 0x10(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	N/A
MOV 0x18(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	N/A
VMOVSS %XMM8,(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM7,(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM6,(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (6.3%)
ADD $0x58,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 401b03 <Step10_orig+0x183>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VXORPS %XMM6,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPS %XMM6,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPS %XMM6,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 401b03 <Step10_orig+0x183>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_no_fastmath

Source file and lines	Step10_orig.c:10-41
Module	exec

The function is defined in /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/Step10_orig.c:10,17-41.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.50 to 4.00 cycles (1.87x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	50
nb uops	45
loop length	175
used x86 registers	14
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.50 cycles
front end	7.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.00	1.75	1.75	1.50	2.00	4.33	4.33	4.33	0.00	0.00	0.00	0.00	4.00	4.00
cycles	2.00	1.75	1.75	1.50	2.00	4.33	4.33	4.33	0.00	0.00	0.00	0.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.50
Dispatch	4.33
Overall L1	7.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	42%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	26%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	46%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.50 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (6.40 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 401980

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVSXD %EDI,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB $0x58,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
VMOVSS %XMM0,-0x54(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (6.3%)
MOV %R8,-0x70(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x78(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (12.5%)
VMOVSS %XMM1,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM2,-0x5c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM3,-0x60(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM4,-0x64(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (6.3%)
TEST %EBX,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JLE 401b70 <Step10_orig+0x1f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
VXORPS %XMM6,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x2,%RBX	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVAPS %XMM6,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPS %XMM6,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x78(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	N/A
MOV 0x10(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	N/A
MOV 0x18(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	N/A
VMOVSS %XMM8,(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM7,(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM6,(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (6.3%)
ADD $0x58,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 401b03 <Step10_orig+0x183>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VXORPS %XMM6,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPS %XMM6,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPS %XMM6,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 401b03 <Step10_orig+0x183>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A

Name	Coverage (%)	Time (s)
▼Step10_orig–	14.63	11.60
○Loop 3 - Step10_orig.c:19-35 - exec	14.63	11.59

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code