OV - exec - Function main._omp

	Function: main._omp_fn.1	Module: exec	Source: main.c:139-146	Coverage (incl. loops): 0.02% \| (excl. loops): 0.01%

/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c: 139 - 146

--------------------------------------------------------------------------------

139:     #pragma omp parallel for private( dx1, dy1, dz1 )

140:       for ( i = 0; i < count; ++i)

141:       {

142:         Step10_orig( n, xx[i], yy[i], zz[i], fsrrmax2, mp_rsm2, xx, yy, zz, mass, &dx1, &dy1, &dz1 );

143:

144:         vx1[i] = vx1[i] + dx1 * fcoeff;

145:         vy1[i] = vy1[i] + dy1 * fcoeff;

146:         vz1[i] = vz1[i] + dz1 * fcoeff;

0x401570 PUSH	%RBP

0x401571 MOV	%RSP,%RBP

0x401574 PUSH	%R15

0x401576 PUSH	%R14

0x401578 PUSH	%R13

0x40157a PUSH	%R12

0x40157c PUSH	%RBX

0x40157d MOV	%RDI,%R13

0x401580 SUB	$0x38,%RSP

0x401584 CALL	401050 <omp_get_num_threads@plt>

0x401589 MOV	%EAX,%EBX

0x40158b CALL	401080 <omp_get_thread_num@plt>

0x401590 MOV	%EAX,%R10D

0x401593 MOV	0x10(%R13),%EAX

0x401597 CLTD

0x401598 IDIV	%EBX

0x40159a CMP	%EDX,%R10D

0x40159d JL	4018d0

0x4015a3 IMUL	%EAX,%R10D

0x4015a7 ADD	%EDX,%R10D

0x4015aa LEA	(%RAX,%R10,1),%EBX

0x4015ae CMP	%EBX,%R10D

0x4015b1 JGE	4018b6

0x4015b7 MOVSXD	%R10D,%R11

0x4015ba VMOVSS	0x4(%R13),%XMM4

0x4015c0 VMOVSS	0x8(%R13),%XMM5

0x4015c6 VMOVSS	(%R13),%XMM3

0x4015cc VMOVSS	0x58aaa0(,%R11,4),%XMM0

0x4015d6 MOV	0xc(%R13),%EDI

0x4015da VMOVSS	0x64dfa0(,%R11,4),%XMM2

0x4015e4 LEA	-0x34(%RBP),%R14

0x4015e8 VMOVSS	0x5ec520(,%R11,4),%XMM1

0x4015f2 LEA	-0x38(%RBP),%R13

0x4015f6 LEA	-0x3c(%RBP),%R9

0x4015fa MOV	$0x64dfa0,%ECX

0x4015ff MOV	$0x529020,%R8D

0x401605 MOV	$0x5ec520,%EDX

0x40160a MOV	$0x58aaa0,%ESI

0x40160f MOV	%R11,%R15

0x401612 NOT	%R15

0x401615 ADD	%EBX,%R15D

0x401618 VMOVSS	%XMM4,-0x48(%RBP)

0x40161d MOV	%EDI,-0x44(%RBP)

0x401620 AND	$0x1,%R15D

0x401624 VMOVSS	%XMM5,-0x50(%RBP)

0x401629 VMOVSS	%XMM3,-0x4c(%RBP)

0x40162e PUSH	%R14

0x401630 PUSH	%R13

0x401632 MOV	%R11,-0x58(%RBP)

0x401636 CALL	401980 <Step10_orig>

0x40163b MOV	-0x58(%RBP),%RCX

0x40163f VMOVSS	-0x50(%RBP),%XMM4

0x401644 VMOVSS	-0x3c(%RBP),%XMM0

0x401649 VMOVSS	-0x38(%RBP),%XMM1

0x40164e VMOVSS	-0x34(%RBP),%XMM2

0x401653 LEA	0x1(%RCX),%R12

0x401657 VFMADD213SS	0x4c75a0(,%RCX,4),%XMM4,%XMM0

0x401661 VFMADD213SS	0x465b20(,%RCX,4),%XMM4,%XMM1

0x40166b VMOVSS	%XMM0,0x4c75a0(,%RCX,4)

0x401674 VMOVSS	%XMM1,0x465b20(,%RCX,4)

0x40167d VFMADD213SS	0x4040a0(,%RCX,4),%XMM4,%XMM2

0x401687 VMOVSS	%XMM2,0x4040a0(,%RCX,4)

0x401690 POP	%R9

0x401692 POP	%R11

0x401694 CMP	%R12D,%EBX

0x401697 JLE	4018b6

0x40169d MOV	%RCX,-0x58(%RBP)

0x4016a1 TEST	%R15D,%R15D

0x4016a4 JE	401760

0x4016aa VMOVSS	0x58aaa0(,%R12,4),%XMM0

0x4016b4 VMOVSS	%XMM4,-0x50(%RBP)

0x4016b9 VMOVSS	-0x4c(%RBP),%XMM3

0x4016be VMOVSS	-0x48(%RBP),%XMM4

0x4016c3 VMOVSS	0x64dfa0(,%R12,4),%XMM2

0x4016cd VMOVSS	0x5ec520(,%R12,4),%XMM1

0x4016d7 MOV	-0x44(%RBP),%EDI

0x4016da MOV	$0x5ec520,%EDX

0x4016df PUSH	%R14

0x4016e1 MOV	$0x58aaa0,%ESI

0x4016e6 PUSH	%R13

0x4016e8 LEA	-0x3c(%RBP),%R9

0x4016ec MOV	$0x529020,%R8D

0x4016f2 MOV	$0x64dfa0,%ECX

0x4016f7 CALL	401980 <Step10_orig>

0x4016fc MOV	-0x58(%RBP),%RSI

0x401700 VMOVSS	-0x50(%RBP),%XMM4

0x401705 VMOVSS	-0x3c(%RBP),%XMM3

0x40170a VMOVSS	-0x38(%RBP),%XMM6

0x40170f VFMADD213SS	0x4c75a0(,%R12,4),%XMM4,%XMM3

0x401719 VFMADD213SS	0x465b20(,%R12,4),%XMM4,%XMM6

0x401723 VMOVSS	%XMM3,0x4c75a0(,%R12,4)

0x40172d VMOVSS	%XMM6,0x465b20(,%R12,4)

0x401737 VMOVSS	-0x34(%RBP),%XMM7

0x40173c VFMADD213SS	0x4040a0(,%R12,4),%XMM4,%XMM7

0x401746 VMOVSS	%XMM7,0x4040a0(,%R12,4)

0x401750 POP	%RAX

0x401751 POP	%RDX

0x401752 LEA	0x2(%RSI),%R12

0x401756 CMP	%R12D,%EBX

0x401759 JLE	4018b6

0x40175f NOP

(2) 0x401760 VMOVSS	0x58aaa0(,%R12,4),%XMM0

(2) 0x40176a VMOVSS	%XMM4,-0x58(%RBP)

(2) 0x40176f VMOVSS	0x64dfa0(,%R12,4),%XMM2

(2) 0x401779 VMOVSS	0x5ec520(,%R12,4),%XMM1

(2) 0x401783 VMOVSS	-0x48(%RBP),%XMM4

(2) 0x401788 VMOVSS	-0x4c(%RBP),%XMM3

(2) 0x40178d MOV	-0x44(%RBP),%EDI

(2) 0x401790 LEA	0x1(%R12),%R15

(2) 0x401795 PUSH	%R14

(2) 0x401797 LEA	-0x3c(%RBP),%R9

(2) 0x40179b PUSH	%R13

(2) 0x40179d MOV	$0x529020,%R8D

(2) 0x4017a3 MOV	$0x64dfa0,%ECX

(2) 0x4017a8 MOV	$0x5ec520,%EDX

(2) 0x4017ad MOV	$0x58aaa0,%ESI

(2) 0x4017b2 CALL	401980 <Step10_orig>

(2) 0x4017b7 VMOVSS	0x58aaa0(,%R15,4),%XMM0

(2) 0x4017c1 VMOVSS	-0x48(%RBP),%XMM4

(2) 0x4017c6 VMOVSS	-0x4c(%RBP),%XMM3

(2) 0x4017cb VMOVSS	0x64dfa0(,%R15,4),%XMM2

(2) 0x4017d5 VMOVSS	0x5ec520(,%R15,4),%XMM1

(2) 0x4017df MOV	$0x529020,%R8D

(2) 0x4017e5 LEA	-0x3c(%RBP),%R9

(2) 0x4017e9 MOV	-0x44(%RBP),%EDI

(2) 0x4017ec VMOVSS	-0x58(%RBP),%XMM9

(2) 0x4017f1 VMOVSS	-0x3c(%RBP),%XMM8

(2) 0x4017f6 VFMADD213SS	0x4c75a0(,%R12,4),%XMM9,%XMM8

(2) 0x401800 VMOVSS	-0x38(%RBP),%XMM10

(2) 0x401805 VMOVSS	%XMM8,0x4c75a0(,%R12,4)

(2) 0x40180f VFMADD213SS	0x465b20(,%R12,4),%XMM9,%XMM10

(2) 0x401819 VMOVSS	-0x34(%RBP),%XMM11

(2) 0x40181e VMOVSS	%XMM10,0x465b20(,%R12,4)

(2) 0x401828 VFMADD213SS	0x4040a0(,%R12,4),%XMM9,%XMM11

(2) 0x401832 MOV	$0x5ec520,%EDX

(2) 0x401837 VMOVSS	%XMM11,0x4040a0(,%R12,4)

(2) 0x401841 POP	%RCX

(2) 0x401842 POP	%RSI

(2) 0x401843 MOV	$0x64dfa0,%ECX

(2) 0x401848 PUSH	%R14

(2) 0x40184a MOV	$0x58aaa0,%ESI

(2) 0x40184f PUSH	%R13

(2) 0x401851 ADD	$0x2,%R12

(2) 0x401855 CALL	401980 <Step10_orig>

(2) 0x40185a VMOVSS	-0x58(%RBP),%XMM4

(2) 0x40185f VMOVSS	-0x3c(%RBP),%XMM12

(2) 0x401864 VMOVSS	-0x38(%RBP),%XMM13

(2) 0x401869 VMOVSS	-0x34(%RBP),%XMM14

(2) 0x40186e VFMADD213SS	0x4c75a0(,%R15,4),%XMM4,%XMM12

(2) 0x401878 VFMADD213SS	0x465b20(,%R15,4),%XMM4,%XMM13

(2) 0x401882 VMOVSS	%XMM12,0x4c75a0(,%R15,4)

(2) 0x40188c VMOVSS	%XMM13,0x465b20(,%R15,4)

(2) 0x401896 VFMADD213SS	0x4040a0(,%R15,4),%XMM4,%XMM14

(2) 0x4018a0 VMOVSS	%XMM14,0x4040a0(,%R15,4)

(2) 0x4018aa POP	%RDI

(2) 0x4018ab POP	%R8

(2) 0x4018ad CMP	%R12D,%EBX

(2) 0x4018b0 JG	401760

0x4018b6 LEA	-0x28(%RBP),%RSP

0x4018ba POP	%RBX

0x4018bb POP	%R12

0x4018bd POP	%R13

0x4018bf POP	%R14

0x4018c1 POP	%R15

0x4018c3 POP	%RBP

0x4018c4 RET

0x4018c5 NOPW	%CS:(%RAX,%RAX,1)

0x4018d0 INC	%EAX

0x4018d2 XOR	%EDX,%EDX

0x4018d4 JMP	4015a3

0x4018d9 NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○99.66	gomp_thread_start	team.c:130	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_no_fastmath

Source file and lines	main.c:139-146
Module	exec

The function is defined in /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139-146.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.17 to 12.00 cycles (1.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 6% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 19.17 to 1.73 cycles (11.08x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 6 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

Step10_orig: 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:142
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:142
omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 12 FP arithmetical operations:

6: addition or subtraction (all inside FMA instructions)
6: multiply (all inside FMA instructions)

The binary function is loading 128 bytes (32 single precision FP elements). The binary function is storing 60 bytes (15 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	114
nb uops	115
loop length	538
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.17 cycles
front end	19.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	9.00	9.00	8.75	8.75	6.50	15.67	15.67	15.67	3.00	3.00	0.00	0.00	5.00	5.00
cycles	9.00	9.00	8.75	8.75	6.50	15.67	15.67	15.67	3.00	3.00	0.00	0.00	5.00	5.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	19.17
Dispatch	15.67
DIV/SQRT	6.00
Overall L1	19.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	7%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	9%
fma	6%
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.17 cycles. At this rate:

6% of peak load performance is reached (6.68 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (3.13 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 19.17 to 15.67 cycles (1.22x speedup).

ASM code

In the binary file, the address of the function is: 401570

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x38,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CALL 401050 <omp_get_num_threads@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 401080 <omp_get_thread_num@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%R13),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	N/A
CLTD																		scal (6.3%)
IDIV %EBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JL 4018d0 <main._omp_fn.1+0x360>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%R10D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %EDX,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%R10,1),%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %EBX,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JGE 4018b6 <main._omp_fn.1+0x346>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSXD %R10D,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSS 0x4(%R13),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x8(%R13),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS (%R13),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x58aaa0(,%R11,4),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOV 0xc(%R13),%EDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (6.3%)
VMOVSS 0x64dfa0(,%R11,4),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
LEA -0x34(%RBP),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSS 0x5ec520(,%R11,4),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
LEA -0x38(%RBP),%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x3c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x64dfa0,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x529020,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x5ec520,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x58aaa0,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R11,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOT %R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD %EBX,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
VMOVSS %XMM4,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
MOV %EDI,-0x44(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
AND $0x1,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
VMOVSS %XMM5,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM3,-0x4c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %R11,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 401980 <Step10_orig>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
MOV -0x58(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	N/A
VMOVSS -0x50(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x3c(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x38(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x34(%RBP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x1(%RCX),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VFMADD213SS 0x4c75a0(,%RCX,4),%XMM4,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VFMADD213SS 0x465b20(,%RCX,4),%XMM4,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VMOVSS %XMM0,0x4c75a0(,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM1,0x465b20(,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
VFMADD213SS 0x4040a0(,%RCX,4),%XMM4,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VMOVSS %XMM2,0x4040a0(,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
POP %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CMP %R12D,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JLE 4018b6 <main._omp_fn.1+0x346>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RCX,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (12.5%)
TEST %R15D,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JE 401760 <main._omp_fn.1+0x1f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSS 0x58aaa0(,%R12,4),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS %XMM4,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
VMOVSS -0x4c(%RBP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x48(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x64dfa0(,%R12,4),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x5ec520(,%R12,4),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOV -0x44(%RBP),%EDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV $0x5ec520,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x58aaa0,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LEA -0x3c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x529020,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x64dfa0,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CALL 401980 <Step10_orig>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
MOV -0x58(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	N/A
VMOVSS -0x50(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x3c(%RBP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x38(%RBP),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VFMADD213SS 0x4c75a0(,%R12,4),%XMM4,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VFMADD213SS 0x465b20(,%R12,4),%XMM4,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VMOVSS %XMM3,0x4c75a0(,%R12,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM6,0x465b20(,%R12,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
VMOVSS -0x34(%RBP),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VFMADD213SS 0x4040a0(,%R12,4),%XMM4,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VMOVSS %XMM7,0x4040a0(,%R12,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
POP %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA 0x2(%RSI),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R12D,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JLE 4018b6 <main._omp_fn.1+0x346>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
LEA -0x28(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 4015a3 <main._omp_fn.1+0x33>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_no_fastmath

Source file and lines	main.c:139-146
Module	exec

The function is defined in /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139-146.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 6 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Step10_orig: 2 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:142
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:142
omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c:139

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 12 FP arithmetical operations:

6: addition or subtraction (all inside FMA instructions)
6: multiply (all inside FMA instructions)

The binary function is loading 128 bytes (32 single precision FP elements). The binary function is storing 60 bytes (15 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	114
nb uops	115
loop length	538
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.17 cycles
front end	19.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	9.00	9.00	8.75	8.75	6.50	15.67	15.67	15.67	3.00	3.00	0.00	0.00	5.00	5.00
cycles	9.00	9.00	8.75	8.75	6.50	15.67	15.67	15.67	3.00	3.00	0.00	0.00	5.00	5.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	19.17
Dispatch	15.67
DIV/SQRT	6.00
Overall L1	19.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	7%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	9%
fma	6%
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.17 cycles. At this rate:

6% of peak load performance is reached (6.68 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (3.13 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 401570

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x38,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CALL 401050 <omp_get_num_threads@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 401080 <omp_get_thread_num@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%R13),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	N/A
CLTD																		scal (6.3%)
IDIV %EBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JL 4018d0 <main._omp_fn.1+0x360>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%R10D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %EDX,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%R10,1),%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %EBX,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JGE 4018b6 <main._omp_fn.1+0x346>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSXD %R10D,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSS 0x4(%R13),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x8(%R13),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS (%R13),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x58aaa0(,%R11,4),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOV 0xc(%R13),%EDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (6.3%)
VMOVSS 0x64dfa0(,%R11,4),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
LEA -0x34(%RBP),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSS 0x5ec520(,%R11,4),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
LEA -0x38(%RBP),%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x3c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x64dfa0,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x529020,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x5ec520,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x58aaa0,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R11,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOT %R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD %EBX,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
VMOVSS %XMM4,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
MOV %EDI,-0x44(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
AND $0x1,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
VMOVSS %XMM5,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM3,-0x4c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %R11,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 401980 <Step10_orig>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
MOV -0x58(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	N/A
VMOVSS -0x50(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x3c(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x38(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x34(%RBP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x1(%RCX),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VFMADD213SS 0x4c75a0(,%RCX,4),%XMM4,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VFMADD213SS 0x465b20(,%RCX,4),%XMM4,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VMOVSS %XMM0,0x4c75a0(,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM1,0x465b20(,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
VFMADD213SS 0x4040a0(,%RCX,4),%XMM4,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VMOVSS %XMM2,0x4040a0(,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
POP %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CMP %R12D,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JLE 4018b6 <main._omp_fn.1+0x346>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RCX,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (12.5%)
TEST %R15D,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JE 401760 <main._omp_fn.1+0x1f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSS 0x58aaa0(,%R12,4),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS %XMM4,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
VMOVSS -0x4c(%RBP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x48(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x64dfa0(,%R12,4),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS 0x5ec520(,%R12,4),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOV -0x44(%RBP),%EDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV $0x5ec520,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x58aaa0,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LEA -0x3c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x529020,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x64dfa0,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CALL 401980 <Step10_orig>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
MOV -0x58(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	N/A
VMOVSS -0x50(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x3c(%RBP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS -0x38(%RBP),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VFMADD213SS 0x4c75a0(,%R12,4),%XMM4,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VFMADD213SS 0x465b20(,%R12,4),%XMM4,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VMOVSS %XMM3,0x4c75a0(,%R12,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
VMOVSS %XMM6,0x465b20(,%R12,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
VMOVSS -0x34(%RBP),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (6.3%)
VFMADD213SS 0x4040a0(,%R12,4),%XMM4,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VMOVSS %XMM7,0x4040a0(,%R12,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (6.3%)
POP %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA 0x2(%RSI),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R12D,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JLE 4018b6 <main._omp_fn.1+0x346>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
LEA -0x28(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 4015a3 <main._omp_fn.1+0x33>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main._omp_fn.1–	0.02	0.02
○Loop 2 - main.c:142-146 - exec	0.01	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code