	*************************************************
	*                                               *
	*          ONE-View report generation           *
	*                                               *
	*************************************************

[MAQAO] Info: Experiment configuration summary is available adding -dbg=1 in command line

* [MAQAO] Warning: Experiment directory /beegfs/hackathon/users/eoseret/qaas_runs_test/179-075-5378/intel/TeaLeaf/run/oneview_runs/compilers/aocc_2/oneview_results_1790757475 already exists and is reused.
           It can be replaced using --replace in the command line.
[MAQAO] Info: 
[MAQAO] Info: START THE APPLICATION PROFILING
[MAQAO] Info: -> RUNNING THE PROFILER...
[MAQAO] Info:   LPROF has already been run
[MAQAO] Info: STOP THE APPLICATION PROFILING
[MAQAO] Info: 
[MAQAO] Info: START FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: STOP FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: 
[MAQAO] Info: START THE REPORT GENERATION
[MAQAO] Info: -> ONE-VIEW EXPERIMENT DIRECTORY: /beegfs/hackathon/users/eoseret/qaas_runs_test/179-075-5378/intel/TeaLeaf/run/oneview_runs/compilers/aocc_2/oneview_results_1790757475


+====================================================================================================================+
+                                                    1  -  GLOBAL                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             1.1  -  Experiment Summary                                             +
+--------------------------------------------------------------------------------------------------------------------+

  Application:			/beegfs/hackathon/users/eoseret/qaas_runs_test/179-075-5378/intel/TeaLeaf/run/binaries/aocc_2/exec
  Timestamp:			2026-09-30 10:37:55
  Universal Timestamp:		1790757475
  Experiment Type:		MPI; OpenMP; Throughput; 
  Machine:			ins01.benchmarkcenter.megware.com
  Architecture:			x86_64
  Micro Architecture:		ZEN_V4
  Model Name:			AMD EPYC 9654 96-Core Processor
  Cache Size:			1024 KB
  Number of Cores:		96
  OS Version:			Linux 5.14.0-687.29.1.el9_8.x86_64 #1 SMP PREEMPT_DYNAMIC Thu Jul 23 16:18:48 EDT 2026
  Compilation Options:		
		exec: AMD clang version 17.0.6 (CLANG: AOCC_5.1.0-Build#1994 2025_12_23) /cluster/comp/aocc/5.1.0/bin/clang-17 --driver-mode=g++ -D USE_OMP -I /beegfs/hackathon/users/eoseret/qaas_runs_test/179-075-5378/intel/TeaLeaf/build/TeaLeaf/src/omp -I /beegfs/hackathon/users/eoseret/qaas_runs_test/179-075-5378/intel/TeaLeaf/build/aocc_2/generated -I /beegfs/hackathon/users/eoseret/qaas_runs_test/179-075-5378/intel/TeaLeaf/build/TeaLeaf/driver -O3 -march=znver4 -mprefer-vector-width=512 -ffast-math -g -fno-omit-frame-pointer -fcf-protection=none -nopie -grecord-command-line -D NDEBUG -std=c++17 -O3 -Wall -fopenmp=libomp -MD -MT CMakeFiles/tealeaf.dir/src/omp/cg.cpp.o -MF CMakeFiles/tealeaf.dir/src/omp/cg.cpp.o.d -o CMakeFiles/tealeaf.dir/src/omp/cg.cpp.o -c /beegfs/hackathon/users/eoseret/qaas_runs_test/179-075-5378/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp -I /cluster/hpcx/2.50/ompi5-aocc-mt/include -I /cluster/hpcx/2.50/ompi5-aocc-mt/include/openmpi 
  Number of processes observed:	8
  Number of threads observed:	192
  MAQAO version:		2026.1.0
  MAQAO build:			6d1be1d51c1e63266254997eb301734a7264775d::20260810-150026




+--------------------------------------------------------------------------------------------------------------------+
+                                               1.2  -  Global Metrics                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Total Time:				14.65 s
  Max (Thread Active Time):		14.41 s
  Average Active Time:			13.77 s
  Activity Ratio:			99.9 %
  Average number of active threads:	180.446
  Affinity Stability:			99.7 %
  Time spent in analyzed loops:		48.3 %
  Time spent in analyzed innermost loops: 47.7 %
  Time spent in user code:		48.9 %
  Compilation Options Score:		100
  Array Access Efficiency:		99.2 %

   Potential Speedups
  ----------------------------------------------------
  Perfect Flow Complexity:		1.00
  Perfect OpenMP/MPI/Pthread/TBB:	1.31
  Perfect OpenMP/MPI/Pthread/TBB + Load Distribution:	2.05
  If No Scalar Integer:
      Potential Speedup:		1.02
      Nb Loops to get 80%:		2
  If FP Vectorized:
      Potential Speedup:		1.00
      Nb Loops to get 80%:		3
  If Fully Vectorized:
      Potential Speedup:		1.00
      Nb Loops to get 80%:		8
  If Only FP Arithmetic:
      Potential Speedup:		1.12
      Nb Loops to get 80%:		3




+--------------------------------------------------------------------------------------------------------------------+
+                                             1.3  -  Potential Speedups                                             +
+--------------------------------------------------------------------------------------------------------------------+

  If No Scalar Integer:
      Number of loops   | 1      | 7      | 14     | 20     | 28     | 
      Cumulated Speedup | 1.0155 | 1.0194 | 1.0194 | 1.0194 | 1.0194 | 
  Top 5 loops:
    exec - 24:	1.0155
    exec - 28:	1.0173
    exec - 23:	1.0189
    exec - 32:	1.0194
    exec - 165:	1.0194

  If FP Vectorized:
      Number of loops   | 1      | 7      | 14     | 20     | 28     | 
      Cumulated Speedup | 1.0003 | 1.0004 | 1.0004 | 1.0004 | 1.0004 | 
  Top 5 loops:
    exec - 30:	1.0003
    exec - 28:	1.0003
    exec - 23:	1.0004
    exec - 101:	1.0004
    exec - 165:	1.0004

  If Fully Vectorized:
      Number of loops   | 1      | 7      | 14     | 20     | 28     | 
      Cumulated Speedup | 1.0006 | 1.0036 | 1.0048 | 1.0048 | 1.0048 | 
  Top 5 loops:
    exec - 30:	1.0006
    exec - 32:	1.0011
    exec - 128:	1.0017
    exec - 112:	1.0022
    exec - 108:	1.0028

  If Only FP Arithmetic:
      Number of loops   | 1      | 7      | 14     | 20     | 28     | 
      Cumulated Speedup | 1.0538 | 1.1148 | 1.1165 | 1.1168 | 1.1168 | 
  Top 5 loops:
    exec - 24:	1.0538
    exec - 33:	1.0894
    exec - 29:	1.1081
    exec - 23:	1.1102
    exec - 28:	1.1123



+====================================================================================================================+
+                                                   2  -  SUMMARY                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             2.1  -  EXPERIMENT QUALITY                                             +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Application profile is long enough (14.41 s)
To have good quality measurements, it is advised that the application profiling time is greater than 10 seconds.

  [3 / 3] Most of time spent in analyzed modules comes from functions with source/debug info
-g option gives access to debugging informations, such are source locations.

  [2.9979564189945 / 3] Most of time spent in analyzed modules (99.93%) comes from functions compiled with architecture specialization option
-march=znver4


  [3 / 3] Most of time spent in analyzed modules comes from functions with compilation options informations and
-fno-omit-frame-pointer is present
-fno-omit-frame-pointer improves the accuracy of callchains found during the application profiling.

  [3 / 3] Optimization level option is correctly used


  [3 / 3] Host configuration allows retrieval of all necessary metrics.


  [2 / 2] Application is correctly profiled ("Others" category represents 0.20 % of the execution time)
To have a representative profiling, it is advised that the category "Others" represents less than 20% of the execution
time in order to analyze as much as possible of the user code

  [1 / 1] Lstopo present. The Topology lstopo report will be generated.



+--------------------------------------------------------------------------------------------------------------------+
+                                                2.2  -  CODE QUALITY                                                +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Enough time of the experiment time spent in analyzed loops (48.29%)
If the time spent in analyzed loops is less than 30%, standard loop optimizations will have a limited impact on
application performances.

  [4 / 4] Threads activity is good
On average, more than 93.98% of observed threads are actually active 

  [4 / 4] CPU activity is good
CPU cores are active 99.87% of time

  [4 / 4] Loop profile is not flat
At least one loop coverage is greater than 4% (23.47%), representing an hotspot for the application

  [4 / 4] Enough time of the experiment time spent in analyzed innermost loops (47.74%)
If the time spent in analyzed innermost loops is less than 15%, standard innermost loop optimizations such as
vectorisation will have a limited impact on application performances.

  [4 / 4] Affinity is good (99.72%)
Threads are not migrating to CPU cores: probably successfully pinned

  [3 / 3] Less than 10% (0.00%) is spend in BLAS1 operations
It could be more efficient to inline by hand BLAS1 operations

  [0 / 3] Too many functions do not use all threads
Functions running on a reduced number of threads (typically sequential code) cover at least 10% of application
walltime (38.78%). Check both "Max Inclusive Time Over Threads" and "Nb Threads" in Functions or Loops tabs and
consider parallelizing sequential regions or improving parallelization of regions running on a reduced number of
threads

  [3 / 3] Cumulative Outermost/In between loops coverage (0.55%) lower than cumulative innermost loop coverage (47.74%)
Having cumulative Outermost/In between loops coverage greater than cumulative innermost loop coverage will make loop
optimization more complex

  [2 / 2] Less than 10% (0.00%) is spend in BLAS2 operations
BLAS2 calls usually could make a poor cache usage and could benefit from inlining.

  [2 / 2] Less than 10% (0.00%) is spend in Libm/SVML (special functions)



+--------------------------------------------------------------------------------------------------------------------+
+                                               2.3  -  LOOPS OVERVIEW                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Top 5 loops:
   + exec - 24  :
     analysis: Execution Time: 23 % - Vectorization Ratio: 100.00 % - Vector Length Use: 100.00 %

   + exec - 29  :
     analysis: Execution Time: 15 % - Vectorization Ratio: 100.00 % - Vector Length Use: 100.00 %

   + exec - 33  :
     analysis: Execution Time: 7 % - Vectorization Ratio: 100.00 % - Vector Length Use: 100.00 %

   + exec - 28  :
     analysis: Execution Time: 0 % - Vectorization Ratio: 33.33 % - Vector Length Use: 24.11 %
     Loop Computation Issues: 6
        [4] [SA] Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA - Reorganize
            arithmetic expressions to exhibit potential for FMA. This issue costs 4 points.
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.
     Control Flow Issues: 20
        [18] [SA] Too many paths (14 paths) - Simplify control structure. There are 14 issues ( = paths) costing 1
            point each with a malus of 4 points.
        [2] [SA] Non innermost loop (Outermost) - Collapse loop with innermost ones. This issue costs 2 points.
     Data Access Issues: 9
        [7] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, SHUFFLE/PERM, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 7 issues (= instructions) costing 1
            point each.
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 20
        [18] [SA] Too many paths (14 paths) - Simplify control structure. There are 14 issues ( = paths) costing 1
            point each with a malus of 4 points.
        [2] [SA] Non innermost loop (Outermost) - Collapse loop with innermost ones. This issue costs 2 points.
     Inefficient Vectorization: 7
        [7] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, SHUFFLE/PERM, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 7 issues (= instructions) costing 1
            point each.

   + exec - 23  :
     analysis: Execution Time: 0 % - Vectorization Ratio: 22.22 % - Vector Length Use: 18.61 %
     Loop Computation Issues: 6
        [4] [SA] Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA - Reorganize
            arithmetic expressions to exhibit potential for FMA. This issue costs 4 points.
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.
     Control Flow Issues: 19
        [17] [SA] Too many paths (13 paths) - Simplify control structure. There are 13 issues ( = paths) costing 1
            point each with a malus of 4 points.
        [2] [SA] Non innermost loop (Outermost) - Collapse loop with innermost ones. This issue costs 2 points.
     Data Access Issues: 7
        [5] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, SHUFFLE/PERM) - Simplify
            data access and try to get stride 1 access. There are 5 issues (= instructions) costing 1 point each.
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 19
        [17] [SA] Too many paths (13 paths) - Simplify control structure. There are 13 issues ( = paths) costing 1
            point each with a malus of 4 points.
        [2] [SA] Non innermost loop (Outermost) - Collapse loop with innermost ones. This issue costs 2 points.
     Inefficient Vectorization: 5
        [5] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, SHUFFLE/PERM) - Simplify
            data access and try to get stride 1 access. There are 5 issues (= instructions) costing 1 point each.



+====================================================================================================================+
+                                                 3  -  APPLICATION                                                  +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                               3.1  -  Categorization                                               +
+--------------------------------------------------------------------------------------------------------------------+

   Category | IO     | Exe    | System  | Others  | Memory | String | MPI   | TBB   | OMP   | Pthread | Math  |
  ----------+--------+--------+---------+---------+--------+--------+-------+-------+-------+---------+-------+
   Time (%) | 0.00   | 48.85  | 1.87    | 0.20    | 0.00   | 0.12   | 0.37  | 0.00  | 48.57 | 0.01    | 0.00  |




+--------------------------------------------------------------------------------------------------------------------+
+                                          3.2  -  Function Based Profiling                                          +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Functions              | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 4                         | 84.80                     | 84.80                     |
   4% to 8%                   | 1                         | 7.96                      | 92.76                     |
   2% to 4%                   | 1                         | 2.12                      | 94.88                     |
   1% to 2%                   | 1                         | 1.42                      | 96.30                     |
   0.5% to 1%                 | 0                         | 0.00                      | 96.30                     |
   0.25% to 0.5%              | 1                         | 0.45                      | 96.75                     |
   0.125% to 0.25%            | 5                         | 0.99                      | 97.74                     |
   < 0.125%                   | 210                       | 2.26                      | 100.00                    |




+--------------------------------------------------------------------------------------------------------------------+
+                                            3.3  -  Loop Based Profiling                                            +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Loops                  | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 2                         | 38.97                     | 38.97                     |
   4% to 8%                   | 1                         | 7.75                      | 46.72                     |
   2% to 4%                   | 0                         | 0.00                      | 46.72                     |
   1% to 2%                   | 0                         | 0.00                      | 46.72                     |
   0.5% to 1%                 | 0                         | 0.00                      | 46.72                     |
   0.25% to 0.5%              | 0                         | 0.00                      | 46.72                     |
   0.125% to 0.25%            | 2                         | 0.27                      | 46.98                     |
   < 0.125%                   | 43                        | 0.75                      | 47.74                     |


+====================================================================================================================+
+                                                  4  -  FUNCTIONS                                                   +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                              4.1  -  Top 10 Functions                                              +
+--------------------------------------------------------------------------------------------------------------------+

   Function                                               | Module              | Coverage (%)   | Time (s)       |
  --------------------------------------------------------+---------------------+----------------+----------------+
   cg_calc_w(int, int, int, double*, double const*, do... | exec                | 23.73          | 3.27           |
   __kmp_hyper_barrier_release(barrier_type, kmp_info*... | libomp.so           | 22.74          | 3.13           |
   __kmp_hardware_timestamp                               | libomp.so           | 22.44          | 3.09           |
   cg_calc_ur(int, int, int, double, double*, double*,... | exec                | 15.89          | 2.19           |
   cg_calc_p(int, int, int, double, double*, double co... | exec                | 7.96           | 1.10           |
   __kmp_hyper_barrier_gather(barrier_type, kmp_info*,... | libomp.so           | 2.12           | 0.29           |
   unknown_kernel_region                                  | kernel              | 1.42           | 0.20           |
   __GI___sched_yield                                     | libc.so.6           | 0.45           | 0.06           |
   __kmp_init_implicit_task                               | libomp.so           | 0.25           | 0.04           |
   hmca_bcol_basesmuma_allreduce_intra_fanin_fanout_pr... | hmca_bcol_basesm... | 0.20           | 0.66           |


+====================================================================================================================+
+                                                    5  -  LOOPS                                                     +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                5.1  -  Top 10 Loops                                                +
+--------------------------------------------------------------------------------------------------------------------+

   Loop Id        | Module              | Source Location                                        | Coverage (%)   |
  ----------------+---------------------+--------------------------------------------------------+----------------+
   24             | exec                | cg.cpp:88-90                                           | 23.47          |
   29             | exec                | cg.cpp:111-113                                         | 15.50          |
   33             | exec                | cg.cpp:131-131                                         | 7.75           |
   28             | exec                | cg.cpp:105-108                                         | 0.22           |
   23             | exec                | cg.cpp:83-86                                           | 0.21           |
   122            | exec                | pack_halos.cpp:71-71                                   | 0.13           |
   118            | exec                | pack_halos.cpp:53-53                                   | 0.13           |
   30             | exec                | cg.cpp:111-113                                         | 0.12           |
   34             | exec                | cg.cpp:131-131                                         | 0.10           |
   32             | exec                | cg.cpp:127-128,cg.cpp:131-131                          | 0.06           |





+====================================================================================================================+
+                                                     6  -  CQA                                                      +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                   6.1  -  Loops                                                    +
+--------------------------------------------------------------------------------------------------------------------+





      6.1.1  -  Loop 24 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/179-075-5378/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:88-90.

It is main loop of related source loop which is unrolled by 16 (including vectorization).

      6.1.1.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

65% of peak computational performance is used (15.65 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 15.33 to 14.33 cycles (1.07x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.1.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is fully vectorized, using full register length.


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.1.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by:
 - reading data from caches/RAM (load units are a bottleneck)
 - writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 15.33 to 12.00 cycles (1.28x speedup).


Workaround
 - Read less array elements
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop





      6.1.1.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 80 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.1.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VMOVUPD: 2 occurrences<<list_path_1_complex_1>>



      6.1.1.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

20 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.1.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 240 FP arithmetical operations:
 - 144: addition or subtraction (80 inside FMA instructions)
 - 96: multiply (80 inside FMA instructions)
The binary loop is loading 1312 bytes (164 double precision FP elements).
The binary loop is storing 128 bytes (16 double precision FP elements).


      6.1.1.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.







      6.1.2  -  Loop 29 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/179-075-5378/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:111-113.

It is main loop of related source loop which is unrolled by 32 (including vectorization).

      6.1.2.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

60% of peak computational performance is used (14.40 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.2.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is fully vectorized, using full register length.


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.2.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by:
 - reading data from caches/RAM (load units are a bottleneck)
 - writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 13.33 to 12.00 cycles (1.11x speedup).


Workaround
 - Read less array elements
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop





      6.1.2.1.3  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 96 FMA (fused multiply-add) operations.




      6.1.2.1.4  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VMOVUPD: 8 occurrences<<list_path_1_complex_1>>



      6.1.2.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

12 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.2.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 192 FP arithmetical operations:
 - 96: addition or subtraction (all inside FMA instructions)
 - 96: multiply (all inside FMA instructions)
The binary loop is loading 1024 bytes (128 double precision FP elements).
The binary loop is storing 512 bytes (64 double precision FP elements).


      6.1.2.1.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.







      6.1.3  -  Loop 33 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/179-075-5378/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:131.

It is main loop of related source loop which is unrolled by 32 (including vectorization).

      6.1.3.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

40% of peak computational performance is used (9.60 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.3.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is fully vectorized, using full register length.


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.3.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by:
 - reading data from caches/RAM (load units are a bottleneck)
 - writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 6.67 to 4.00 cycles (1.67x speedup).


Workaround
 - Read less array elements
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop





      6.1.3.1.3  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 32 FMA (fused multiply-add) operations.




      6.1.3.1.4  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VMOVUPD: 4 occurrences<<list_path_1_complex_1>>



      6.1.3.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

4 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.3.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 64 FP arithmetical operations:
 - 32: addition or subtraction (all inside FMA instructions)
 - 32: multiply (all inside FMA instructions)
The binary loop is loading 512 bytes (64 double precision FP elements).
The binary loop is storing 256 bytes (32 double precision FP elements).


      6.1.3.1.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.4  -  Loop 28 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/179-075-5378/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:105-113.

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/179-075-5378/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:105-108.

Warnings:
 - Non-innermost loop: analyzing only self part (ignoring child loops).
 - Ignoring paths for analysis
 - Too many paths. Rerun with max-paths=14
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 14 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.4.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

5% of peak computational performance is used (1.38 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.4.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 27.50 to 7.17 cycles (3.84x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.4.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 24% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 27.50 to 22.55 cycles (1.22x speedup).

Details
33% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 0% of SSE/AVX loads are used in vector version.
 - 0% of SSE/AVX stores are used in vector version.
 - 66% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 26% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.4.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.



No data for this section



      6.1.4.1.4  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - AND: 4 occurrences<<list_path_1_complex_1>>
 - SETA: 1 occurrences<<list_path_1_complex_2>>
 - SETB: 7 occurrences<<list_path_1_complex_3>>



      6.1.4.1.5  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 2 suboptimal vector unaligned load/store instructions.


Details
 - VEXTRACTF128: 2 occurrences<<list_path_1_vec_align_1>>


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.4.1.6  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - MOVZX: 4 occurrences<<list_path_1_cvt_1>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.4.1.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).
4 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.4.1.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 38 FP arithmetical operations:
 - 38: addition or subtraction
The binary loop is loading 316 bytes (39 double precision FP elements).
The binary loop is storing 36 bytes (4 double precision FP elements).


      6.1.4.1.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.







      6.1.5  -  Loop 23 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/179-075-5378/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83-90.

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/179-075-5378/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83-86.

Warnings:
 - Non-innermost loop: analyzing only self part (ignoring child loops).
 - Ignoring paths for analysis
 - Too many paths. Rerun with max-paths=13
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 13 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.5.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

2% of peak computational performance is used (0.62 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.5.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 35.50 to 8.33 cycles (4.26x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.5.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 18% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 35.50 to 29.59 cycles (1.20x speedup).

Details
22% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 0% of SSE/AVX loads are used in vector version.
 - 0% of SSE/AVX stores are used in vector version.
 - 57% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 25% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.5.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.



No data for this section



      6.1.5.1.4  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - AND: 4 occurrences<<list_path_1_complex_1>>
 - SETB: 8 occurrences<<list_path_1_complex_2>>



      6.1.5.1.5  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 2 suboptimal vector unaligned load/store instructions.


Details
 - VEXTRACTF128: 2 occurrences<<list_path_1_vec_align_1>>


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.5.1.6  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - MOVZX: 4 occurrences<<list_path_1_cvt_1>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.5.1.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).
2 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.5.1.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 22 FP arithmetical operations:
 - 22: addition or subtraction
The binary loop is loading 528 bytes (66 double precision FP elements).
The binary loop is storing 112 bytes (14 double precision FP elements).


      6.1.5.1.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.







      6.1.6  -  Loop 122 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/179-075-5378/intel/TeaLeaf/build/TeaLeaf/src/omp/pack_halos.cpp:71.

It is main loop of related source loop which is unrolled by 32 (including vectorization).

      6.1.6.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.6.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is fully vectorized, using full register length.


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.6.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by:
 - reading data from caches/RAM (load units are a bottleneck)
 - writing data to caches/RAM (the store unit is a bottleneck)


Workaround
 - Read less array elements
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop




No data for this section



      6.1.6.1.3  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VMOVUPS: 4 occurrences<<list_path_1_complex_1>>



      6.1.6.1.4  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.6.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.6.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 256 bytes.
The binary loop is storing 256 bytes.







      6.1.7  -  Loop 118 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/179-075-5378/intel/TeaLeaf/build/TeaLeaf/src/omp/pack_halos.cpp:53.

It is main loop of related source loop which is unrolled by 32 (including vectorization).

      6.1.7.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.7.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is fully vectorized, using full register length.


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.7.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by:
 - reading data from caches/RAM (load units are a bottleneck)
 - writing data to caches/RAM (the store unit is a bottleneck)


Workaround
 - Read less array elements
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop




No data for this section



      6.1.7.1.3  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VMOVUPS: 4 occurrences<<list_path_1_complex_1>>



      6.1.7.1.4  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.7.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.7.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 256 bytes.
The binary loop is storing 256 bytes.







      6.1.8  -  Loop 30 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/179-075-5378/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:111-113.

It is intermediate loop of related source loop which is unrolled by 32 (including vectorization).

      6.1.8.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

25% of peak computational performance is used (6.00 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.8.1.1  -  Unrolling/vectorization cost
  ----------------------------------------------------------------------------------------------------------

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details
The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround
 - recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
 - hardcode most frequent values of loop bounds by adding specialized paths.:
  *  For instance, replace for (i=0; i<n; i++) foo(i) with:
switch (n) {
  case (4): for (i=0; i<4; i++) foo(i); break;
  case (6): for (i=0; i<6; i++) foo(i); break;
  default : for (i=0; i<n; i++) foo(i); break;
}



      6.1.8.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).
<<image_4x64_512>>

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.8.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.8.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 12 FMA (fused multiply-add) operations.




      6.1.8.1.5  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 4 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 4 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.8.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

3 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.8.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 24 FP arithmetical operations:
 - 12: addition or subtraction (all inside FMA instructions)
 - 12: multiply (all inside FMA instructions)
The binary loop is loading 128 bytes (16 double precision FP elements).
The binary loop is storing 64 bytes (8 double precision FP elements).


      6.1.8.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.







      6.1.9  -  Loop 34 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/179-075-5378/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:131.

It is intermediate loop of related source loop which is unrolled by 32 (including vectorization).

      6.1.9.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

33% of peak computational performance is used (8.00 out of 24.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.9.1.1  -  Unrolling/vectorization cost
  ----------------------------------------------------------------------------------------------------------

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details
The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround
 - recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
 - hardcode most frequent values of loop bounds by adding specialized paths.:
  *  For instance, replace for (i=0; i<n; i++) foo(i) with:
switch (n) {
  case (4): for (i=0; i<4; i++) foo(i); break;
  case (6): for (i=0; i<6; i++) foo(i); break;
  default : for (i=0; i<n; i++) foo(i); break;
}



      6.1.9.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).
<<image_4x64_512>>

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.9.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by:
 - reading data from caches/RAM (load units are a bottleneck)
 - writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 1.00 to 0.83 cycles (1.20x speedup).


Workaround
 - Read less array elements
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop





      6.1.9.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 4 FMA (fused multiply-add) operations.




      6.1.9.1.5  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 2 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 2 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.9.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

1 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.9.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 8 FP arithmetical operations:
 - 4: addition or subtraction (all inside FMA instructions)
 - 4: multiply (all inside FMA instructions)
The binary loop is loading 64 bytes (8 double precision FP elements).
The binary loop is storing 32 bytes (4 double precision FP elements).


      6.1.9.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.10  -  Loop 32 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/179-075-5378/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:127-131.

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/179-075-5378/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:127-128,131.

Warnings:
 - Non-innermost loop: analyzing only self part (ignoring child loops).
 - Ignoring paths for analysis
 - Too many paths. Rerun with max-paths=9
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 9 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.10.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.10.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 12.67 to 4.00 cycles (3.17x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.10.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
Only 11% of vector register length is used (average across all SSE/AVX instructions).
By vectorizing your loop, you can lower the cost of an iteration from 12.67 to 1.83 cycles (6.91x speedup).

Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.10.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.



No data for this section



      6.1.10.1.4  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - SETA: 1 occurrences<<list_path_1_complex_1>>
 - SETB: 2 occurrences<<list_path_1_complex_2>>



      6.1.10.1.5  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - MOVZX: 1 occurrences<<list_path_1_cvt_1>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.10.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.10.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 159 bytes.
The binary loop is storing 19 bytes.





[MAQAO] Info: STOP THE REPORT GENERATION
[MAQAO] Info: 
[MAQAO] Info: If your application produces files, they can be found in directory "/beegfs/hackathon/users/eoseret/qaas_runs_test/179-075-5378/intel/TeaLeaf/run/oneview_runs/compilers/aocc_2/oneview_run_1790757475"
[MAQAO] Info: 
