Function: .omp_outlined..64 | Module: exec | Source: miniqmc.cpp:411-475 [...] | Coverage: 0.01% |
---|
Function: .omp_outlined..64 | Module: exec | Source: miniqmc.cpp:411-475 [...] | Coverage: 0.01% |
---|
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 62 - 62 |
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62: X[d] = T(0); |
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/refwrap.h: 347 - 347 |
-------------------------------------------------------------------------------- |
347: { return *_M_data; } |
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/stl_algobase.h: 909 - 910 |
-------------------------------------------------------------------------------- |
909: for (; __first != __last; ++__first) |
910: *__first = __value; |
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/stl_vector.h: 100 - 1124 |
-------------------------------------------------------------------------------- |
100: : _M_start(), _M_finish(), _M_end_of_storage() |
[...] |
366: _M_deallocate(_M_impl._M_start, |
367: _M_impl._M_end_of_storage - _M_impl._M_start); |
[...] |
378: return __n != 0 ? _Tr::allocate(_M_impl, __n) : pointer(); |
[...] |
386: if (__p) |
[...] |
395: this->_M_impl._M_start = this->_M_allocate(__n); |
396: this->_M_impl._M_finish = this->_M_impl._M_start; |
397: this->_M_impl._M_end_of_storage = this->_M_impl._M_start + __n; |
[...] |
1124: return *(this->_M_impl._M_start + __n); |
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/stl_uninitialized.h: 748 - 748 |
-------------------------------------------------------------------------------- |
748: for (; __n > 0; --__n, (void) ++__cur) |
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/random.h: 1873 - 1873 |
-------------------------------------------------------------------------------- |
1873: return (__aurng() * (__p.b() - __p.a())) + __p.a(); |
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/alloc_traits.h: 261 - 318 |
-------------------------------------------------------------------------------- |
261: ::new((void*)__p) _Tp(std::forward<_Args>(__args)...); |
[...] |
318: { return __a.allocate(__n); } |
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/unique_ptr.h: 191 - 191 |
-------------------------------------------------------------------------------- |
191: pointer _M_ptr() const noexcept { return std::get<0>(_M_t); } |
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/new_allocator.h: 120 - 158 |
-------------------------------------------------------------------------------- |
120: if (__builtin_expect(__n > this->_M_max_size(), false)) |
[...] |
137: return static_cast<_Tp*>(_GLIBCXX_OPERATOR_NEW(__n * sizeof(_Tp))); |
[...] |
158: _GLIBCXX_OPERATOR_DELETE(_GLIBCXX_SIZED_DEALLOC(__p, __n)); |
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249 |
-------------------------------------------------------------------------------- |
242: ScopeGuard(TIMER& t) : timer(t) { timer.start(); } |
[...] |
249: ~ScopeGuard() { timer.stop(); } |
/usr/lib/gcc/aarch64-linux-gnu/12/../../../../include/c++/12/bits/random.tcc: 404 - 3379 |
-------------------------------------------------------------------------------- |
404: for (size_t __k = 0; __k < (__n - __m); ++__k) |
405: { |
406: _UIntType __y = ((_M_x[__k] & __upper_mask) |
407: | (_M_x[__k + 1] & __lower_mask)); |
408: _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1) |
409: ^ ((__y & 0x01) ? __a : 0)); |
410: } |
411: |
412: for (size_t __k = (__n - __m); __k < (__n - 1); ++__k) |
413: { |
414: _UIntType __y = ((_M_x[__k] & __upper_mask) |
415: | (_M_x[__k + 1] & __lower_mask)); |
416: _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1) |
417: ^ ((__y & 0x01) ? __a : 0)); |
418: } |
419: |
420: _UIntType __y = ((_M_x[__n - 1] & __upper_mask) |
421: | (_M_x[0] & __lower_mask)); |
[...] |
458: if (_M_p >= state_size) |
459: _M_gen_rand(); |
460: |
461: // Calculate o(x(i)). |
462: result_type __z = _M_x[_M_p++]; |
463: __z ^= (__z >> __u) & __d; |
464: __z ^= (__z << __s) & __b; |
465: __z ^= (__z << __t) & __c; |
466: __z ^= (__z >> __l); |
[...] |
3372: __sum += _RealType(__urng() - __urng.min()) * __tmp; |
3373: __tmp *= __r; |
3374: } |
3375: __ret = __sum / __tmp; |
3376: if (__builtin_expect(__ret >= _RealType(1), 0)) |
3377: { |
3378: #if _GLIBCXX_USE_C99_MATH_TR1 |
3379: __ret = std::nextafter(_RealType(1), _RealType(0)); |
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Utilities/StdRandom.h: 102 - 106 |
-------------------------------------------------------------------------------- |
102: for (int i = 0; i < n; ++i) |
103: d[i] = uniform(myRNG); |
104: } |
105: |
106: inline void generate_normal(T* restrict d, int n) { BoxMuller2::generate(*this, d, n); } |
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Drivers/miniqmc.cpp: 411 - 475 |
-------------------------------------------------------------------------------- |
411: #pragma omp parallel for reduction(+ : my_accepted) |
412: for (int iw = 0; iw < nmovers; iw++) |
413: { |
414: auto& els = *mover_list[iw]->els_ptr; |
415: auto& random_th = mover_list[iw]->rng; |
416: auto& wavefunction = mover_list[iw]->wavefunction; |
417: auto& ecp = mover_list[iw]->nlpp; |
418: |
419: ParticlePos delta(nels); |
420: ParticlePos rOnSphere(nknots); |
421: |
422: aligned_vector<RealType> ur(nels); |
423: |
424: Timers[Timer_Diffusion].get().start(); |
425: for (int l = 0; l < nsubsteps; ++l) // drift-and-diffusion |
426: { |
427: random_th.generate_uniform(ur.data(), nels); |
428: random_th.generate_normal(&delta[0][0], nels3); |
429: for (int iel = 0; iel < nels; ++iel) |
430: { |
431: // Compute gradient at the current position |
432: Timers[Timer_evalGrad].get().start(); |
433: PosType grad_now = wavefunction.evalGrad(els, iel); |
434: Timers[Timer_evalGrad].get().stop(); |
435: |
436: // Construct trial move |
437: els.makeMove(iel, delta[iel]); |
438: |
439: // Compute gradient at the trial position |
440: Timers[Timer_ratioGrad].get().start(); |
441: PosType grad_new; |
442: wavefunction.ratioGrad(els, iel, grad_new); |
443: Timers[Timer_ratioGrad].get().stop(); |
444: |
445: // Accept/reject the trial move |
446: if (ur[iel] < accept) // MC |
447: { |
448: // Update position, and update temporary storage |
449: Timers[Timer_Update].get().start(); |
450: wavefunction.acceptMove(els, iel); |
451: Timers[Timer_Update].get().stop(); |
452: els.acceptMove(iel); |
453: my_accepted++; |
454: } |
455: else |
456: { |
457: els.rejectMove(iel); |
458: wavefunction.restore(iel); |
459: } |
460: } // iel |
461: wavefunction.completeUpdates(); |
462: } // substeps |
463: |
464: els.donePbyP(); |
465: |
466: // evaluate Kinetic Energy |
467: wavefunction.evaluateGL(els); |
468: |
469: Timers[Timer_Diffusion].get().stop(); |
470: |
471: // Compute NLPP energy using integral over spherical points |
472: { |
473: ecp.randomize(rOnSphere); // pick random sphere |
474: ScopedTimer local(Timers[Timer_ECP]); |
475: ecp.evaluate(els, wavefunction); |
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 47 - 301 |
-------------------------------------------------------------------------------- |
47: { |
48: if (n) |
[...] |
144: virtual ~Vector() { free(); } |
[...] |
210: if (nAllocated) |
211: { |
212: mAllocator.deallocate(X, nAllocated); |
[...] |
289: T* X = nullptr; |
[...] |
300: X = mAllocator.allocate(n); |
301: nLocal = n; |
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Particle/ParticleAttrib.h: 34 - 34 |
-------------------------------------------------------------------------------- |
34: explicit inline ParticleAttrib(size_t n = 0) : __my_base(n), InUnit(0) {} |
/home/hbollore/qaas-runs/171-284-6744/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/Mallocator.hpp: 76 - 78 |
-------------------------------------------------------------------------------- |
76: if (n == 0) |
77: throw std::runtime_error("Mallocator::deallocate does not accept size 0 allocations."); |
78: free(p); |
0x4098b0 SUB SP, SP, #400 |
0x4098b4 STR D10, [SP, #272] |
0x4098b8 STP D9, D8, [SP, #288] |
0x4098bc STP X29, X30, [SP, #304] |
0x4098c0 STP X28, X27, [SP, #320] |
0x4098c4 STP X26, X25, [SP, #336] |
0x4098c8 STP X24, X23, [SP, #352] |
0x4098cc STP X22, X21, [SP, #368] |
0x4098d0 STP X20, X19, [SP, #384] |
0x4098d4 ADD X29, SP, #304 |
0x4098d8 LDR W8, [X2] |
0x4098dc STR X7, [SP, #88] |
0x4098e0 STR X6, [SP, #152] |
0x4098e4 SUBS W19, W8, #1 |
0x4098e8 STP X5, X3, [SP, #48] |
0x4098ec STR X4, [SP, #120] |
0x4098f0 B.LT 40a368 |
0x4098f4 LDR W20, [X0] |
0x4098f8 MOVZ W8, #1 |
0x4098fc ADRP X0, |
0x409900 ADD X0, X0, #2904 |
0x409904 SUB X3, X29, #48 |
0x409908 STP W19, WZR, [X29, #488] |
0x40990c STUR XZR, [X29, #460] |
0x409910 SUB X4, X29, #20 |
0x409914 SUB X5, X29, #24 |
0x409918 SUB X6, X29, #44 |
0x40991c MOVZ W2, #34 |
0x409920 STUR W8, [X29, #468] |
0x409924 STR W8, [SP] |
0x409928 MOVZ W7, #1 |
0x40992c ORR W1, WZR, W20 |
0x409930 BL 404b00 |
0x409934 LDP W8, W10, [X29, #488] |
0x409938 SBFM X10, X10, #0, #31 |
0x40993c CMP W8, W19 |
0x409940 CSEL W8, W8, W19, #11 |
0x409944 CMP W10, W8 |
0x409948 STUR W8, [X29, #488] |
0x40994c B.GT 40a2dc |
0x409950 LDR X9, [X29, #104] |
0x409954 STR W20, [SP, #12] |
0x409958 MOVZ W20, #45279 |
0x40995c CNTW X25, ALL |
0x409960 CNTD X21, ALL |
0x409964 FMOV D8, #1.0000000 |
0x409968 ADD W8, W8, #1 |
0x40996c MOVZ X24, #2 |
0x409970 MOVZ X23, #3 |
0x409974 MOVK W20, #39176 |
0x409978 MOVZ X19, #399 |
0x40997c STR W8, [SP, #36] |
0x409980 STR X9, [SP, #112] |
0x409984 LDR X9, [X29, #96] |
0x409988 MOVZ X27, #229 |
0x40998c STR X9, [SP, #80] |
0x409990 SUB X9, X29, #96 |
0x409994 ADD X9, X9, #16 |
0x409998 STR X9, [SP, #40] |
0x40999c ORR X9, XZR, X10 |
0x4099a0 B 4099b8 |
(58) 0x4099a4 LDR X9, [SP, #64] |
(58) 0x4099a8 LDR W8, [SP, #36] |
(58) 0x4099ac ADD X9, X9, #1 |
(58) 0x4099b0 CMP W8, W9 |
(58) 0x4099b4 B.EQ 40a2d8 |
(58) 0x4099b8 LDR X8, [SP, #56] |
(58) 0x4099bc LDR X8, [X8] |
(58) 0x4099c0 LDR X28, [X8, X9,LSL #3] |
(58) 0x4099c4 LDR X8, [SP, #120] |
(58) 0x4099c8 LDR X10, [X28, #5064] |
(58) 0x4099cc LDRSW X1, [X8] |
(58) 0x4099d0 MOVZ X8, #24 |
(58) 0x4099d4 STP X8, X10, [SP, #136] |
(58) 0x4099d8 STP X9, X1, [SP, #64] |
(58) 0x4099dc CBZ W1, 409a40 |
(58) 0x4099e0 TBNZ W1, #31, 40a390 |
(58) 0x4099e4 ADD X8, X1, X1,LSL #1 |
(58) 0x4099e8 UBFM X22, X8, #61, #60 |
(58) 0x4099ec ORR X0, XZR, X22 |
(58) 0x4099f0 BL 404a10 |
(58) 0x4099f4 ORR X9, XZR, #3841 |
(58) 0x4099f8 SUB X8, X22, #24 |
(58) 0x4099fc LDR X10, [SP, #136] |
(58) 0x409a00 MOVK X9, #43691 |
(58) 0x409a04 UMULH X8, X8, X9 |
(58) 0x409a08 MOVZ W9, #24 |
(58) 0x409a0c UBFM X8, X8, #4, #63 |
(58) 0x409a10 MADD X2, X8, X9, X10 |
(58) 0x409a14 RDVL X8, #1 |
(58) 0x409a18 CMP X8, #17 |
(58) 0x409a1c B.CS 409a48 |
(58) 0x409a20 ORR W1, WZR, WZR |
(58) 0x409a24 ORR X22, XZR, X0 |
(58) 0x409a28 BL 404a90 |
(58) 0x409a2c LDR X1, [SP, #72] |
(58) 0x409a30 B 409a70 |
0x409a34 HINT #0 |
0x409a38 HINT #0 |
0x409a3c HINT #0 |
(58) 0x409a40 ORR X22, XZR, XZR |
(58) 0x409a44 B 409a70 |
(58) 0x409a48 LDR X1, [SP, #72] |
(58) 0x409a4c WHILELO P0.B, XZR, X2 |
(58) 0x409a50 ORR X8, XZR, XZR |
(58) 0x409a54 DUP Z0.B, #0 |
(58) 0x409a58 ORR X22, XZR, X0 |
(58) 0x409a5c HINT #0 |
(61) 0x409a60 ST1B {Z0.B}, P0, [X22, X8] |
(61) 0x409a64 INCP X8, P0.B |
(61) 0x409a68 WHILELO P0.B, X8, X2 |
(61) 0x409a6c B.MI 409a60 |
(58) 0x409a70 LDR X8, [SP, #48] |
(58) 0x409a74 STR X22, [SP, #96] |
(58) 0x409a78 LDRSW X26, [X8] |
(58) 0x409a7c ADRP X8, |
(58) 0x409a80 ADD X8, X8, #3160 |
(58) 0x409a84 STP X8, X26, [X29, #928] |
(58) 0x409a88 LDR X8, [SP, #40] |
(58) 0x409a8c STP XZR, XZR, [X8] |
(58) 0x409a90 CBZ W26, 409b10 |
(58) 0x409a94 TBNZ W26, #31, 40a390 |
(58) 0x409a98 ADD X8, X26, X26,LSL #1 |
(58) 0x409a9c UBFM X22, X8, #61, #60 |
(58) 0x409aa0 ORR X0, XZR, X22 |
(58) 0x409aa4 BL 404a10 |
(58) 0x409aa8 ORR X9, XZR, #3841 |
(58) 0x409aac SUB X8, X22, #24 |
(58) 0x409ab0 LDR X10, [SP, #136] |
(58) 0x409ab4 STP X26, X0, [X29, #944] |
(58) 0x409ab8 STUR X26, [X29, #424] |
(58) 0x409abc MOVK X9, #43691 |
(58) 0x409ac0 UMULH X8, X8, X9 |
(58) 0x409ac4 MOVZ W9, #24 |
(58) 0x409ac8 UBFM X8, X8, #4, #63 |
(58) 0x409acc MADD X2, X8, X9, X10 |
(58) 0x409ad0 RDVL X8, #1 |
(58) 0x409ad4 CMP X8, #17 |
(58) 0x409ad8 B.CS 409aec |
(58) 0x409adc ORR W1, WZR, WZR |
(58) 0x409ae0 BL 404a90 |
(58) 0x409ae4 LDR X1, [SP, #72] |
(58) 0x409ae8 B 409b10 |
(58) 0x409aec LDR X1, [SP, #72] |
(58) 0x409af0 WHILELO P0.B, XZR, X2 |
(58) 0x409af4 ORR X8, XZR, XZR |
(58) 0x409af8 DUP Z0.B, #0 |
(58) 0x409afc HINT #0 |
(60) 0x409b00 ST1B {Z0.B}, P0, [X0, X8] |
(60) 0x409b04 INCP X8, P0.B |
(60) 0x409b08 WHILELO P0.B, X8, X2 |
(60) 0x409b0c B.MI 409b00 |
(58) 0x409b10 ADRP X8, |
(58) 0x409b14 ADD X8, X8, #3088 |
(58) 0x409b18 STUR WZR, [X29, #452] |
(58) 0x409b1c STP XZR, XZR, [X29, #904] |
(58) 0x409b20 STP XZR, X8, [X29, #920] |
(58) 0x409b24 CBZ W1, 409b60 |
(58) 0x409b28 SUB X0, X29, #120 |
(58) 0x409b2c BL 40c270 |
(58) 0x409b30 LDR X8, [SP, #72] |
(58) 0x409b34 ORR X26, XZR, X0 |
(58) 0x409b38 STUR X0, [X29, #392] |
(58) 0x409b3c UBFM X22, X8, #61, #60 |
(58) 0x409b40 RDVL X8, #1 |
(58) 0x409b44 CMP X8, #17 |
(58) 0x409b48 B.CS 409b6c |
(58) 0x409b4c ORR X0, XZR, X26 |
(58) 0x409b50 ORR W1, WZR, WZR |
(58) 0x409b54 ORR X2, XZR, X22 |
(58) 0x409b58 BL 404a90 |
(58) 0x409b5c B 409b90 |
(58) 0x409b60 ORR X8, XZR, XZR |
(58) 0x409b64 ORR X9, XZR, XZR |
(58) 0x409b68 B 409b98 |
(58) 0x409b6c WHILELO P0.B, XZR, X22 |
(58) 0x409b70 ORR X8, XZR, XZR |
(58) 0x409b74 DUP Z0.B, #0 |
(58) 0x409b78 HINT #0 |
(58) 0x409b7c HINT #0 |
(59) 0x409b80 ST1B {Z0.B}, P0, [X26, X8] |
(59) 0x409b84 INCP X8, P0.B |
(59) 0x409b88 WHILELO P0.B, X8, X22 |
(59) 0x409b8c B.MI 409b80 |
(58) 0x409b90 ADD X8, X26, X22 |
(58) 0x409b94 ADD X9, X26, X22 |
(58) 0x409b98 STP X9, X8, [X29, #912] |
(58) 0x409b9c LDR X8, [SP, #152] |
(58) 0x409ba0 LDR X8, [X8] |
(58) 0x409ba4 LDR X0, [X8, #16] |
(58) 0x409ba8 BL 46c6e0 |
(58) 0x409bac MOVZ W8, #5072 |
(58) 0x409bb0 ADD X8, X28, X8 |
(58) 0x409bb4 STR X8, [SP, #128] |
(58) 0x409bb8 LDR X8, [SP, #88] |
(58) 0x409bbc LDR W8, [X8] |
(58) 0x409bc0 CMP W8, #1 |
(58) 0x409bc4 B.LT 40a228 |
(46) 0x409bc8 LDR X26, [SP, #96] |
(46) 0x409bcc ADD X8, X28, #16 |
(46) 0x409bd0 STR WZR, [SP, #108] |
(46) 0x409bd4 STR X8, [SP, #136] |
(46) 0x409bd8 HINT #0 |
(46) 0x409bdc HINT #0 |
(46) 0x409be0 LDR X8, [SP, #120] |
(46) 0x409be4 LDR W15, [X8] |
(46) 0x409be8 CMP W15, #1 |
(46) 0x409bec B.LT 40a0a4 |
(46) 0x409bf0 LDR D0, [X28, #5024] |
(46) 0x409bf4 LDR D9, [X28, #5016] |
(46) 0x409bf8 LDUR X16, [X29, #392] |
(46) 0x409bfc ORR X26, XZR, XZR |
(46) 0x409c00 FSUB D10, D0, S9 |
(46) 0x409c04 LDR X22, [X28, #5008] |
(49) 0x409c08 CMP X22, #624 |
(49) 0x409c0c B.CC 409dcc |
(49) 0x409c10 SUB W8, W25, #1 |
(49) 0x409c14 MOVZ W11, #227 |
(49) 0x409c18 ORR X9, XZR, XZR |
(49) 0x409c1c PTRUE P2.D, ALL |
(49) 0x409c20 AND X10, X8, X11 |
(49) 0x409c24 EOR X8, X10, X11 |
(49) 0x409c28 ADDVL X11, X28, #1 |
(54) 0x409c2c UBFM X12, X9, #61, #60 |
(54) 0x409c30 ADD X9, X9, X25 |
(54) 0x409c34 ADD X13, X28, X12 |
(54) 0x409c38 ADD X12, X11, X12 |
(54) 0x409c3c LD1D {Z0.D}, P2/Z, [X13, X24,LSL #3] |
(54) 0x409c40 LD1D {Z1.D}, P2/Z, [X12, X24,LSL #3] |
(54) 0x409c44 LD1D {Z3.D}, P2/Z, [X12, X23,LSL #3] |
(54) 0x409c48 LD1D {Z2.D}, P2/Z, [X13, X23,LSL #3] |
(54) 0x409c4c MOVPRFX Z4, Z2 |
(54) 0x409c50 AND Z4.D, Z4.D, #2147483646 |
(54) 0x409c54 MOVPRFX Z5, Z3 |
(54) 0x409c58 AND Z5.D, Z5.D, #2147483646 |
(54) 0x409c5c AND Z0.D, Z0.D, #-2147483648 |
(54) 0x409c60 AND Z1.D, Z1.D, #-2147483648 |
(54) 0x409c64 AND Z3.D, Z3.D, #1 |
(54) 0x409c68 AND Z2.D, Z2.D, #1 |
(54) 0x409c6c ORR Z0.D, Z4.D, Z0.D |
(54) 0x409c70 ORR Z1.D, Z5.D, Z1.D |
(54) 0x409c74 LD1D {Z4.D}, P2/Z, [X13, X19,LSL #3] |
(54) 0x409c78 LD1D {Z5.D}, P2/Z, [X12, X19,LSL #3] |
(54) 0x409c7c CMPEQ P1.D, P2/Z, Z3.D, #0 |
(54) 0x409c80 CMPEQ P0.D, P2/Z, Z2.D, #0 |
(54) 0x409c84 DUP Z2.D, X20 |
(54) 0x409c88 MOVPRFX Z3, Z2 |
(54) 0x409c8c CPY Z3.D, P0/M, #0 |
(54) 0x409c90 CMP X8, X9 |
(54) 0x409c94 LSR Z0.D, Z0.D, #63 |
(54) 0x409c98 LSR Z1.D, Z1.D, #63 |
(54) 0x409c9c CPY Z2.D, P1/M, #0 |
(54) 0x409ca0 EOR Z0.D, Z0.D, Z4.D |
(54) 0x409ca4 EOR Z1.D, Z1.D, Z5.D |
(54) 0x409ca8 EOR Z0.D, Z0.D, Z3.D |
(54) 0x409cac EOR Z1.D, Z1.D, Z2.D |
(54) 0x409cb0 ST1D {Z0.D}, P2, [X13, X24,LSL #3] |
(54) 0x409cb4 ST1D {Z1.D}, P2, [X12, X24,LSL #3] |
(54) 0x409cb8 B.NE 409c2c |
(49) 0x409cbc MOVZ X13, #230 |
(49) 0x409cc0 CBZ X10, 409d04 |
(49) 0x409cc4 LDR X9, [SP, #136] |
(49) 0x409cc8 LDR X9, [X9, X8,LSL #3] |
(57) 0x409ccc ADD X10, X28, X8,LSL #3 |
(57) 0x409cd0 AND X11, X9, #6177 |
(57) 0x409cd4 ADD X8, X8, #1 |
(57) 0x409cd8 CMP X8, #227 |
(57) 0x409cdc LDR X9, [X10, #24] |
(57) 0x409ce0 AND X12, X9, #6015 |
(57) 0x409ce4 ORR X11, X12, X11 |
(57) 0x409ce8 LDR X12, [X10, #3192] |
(57) 0x409cec EOR X11, X12, X11,LSR #1 |
(57) 0x409cf0 SBFM X12, X9, #0, #0 |
(57) 0x409cf4 AND X12, X12, X20 |
(57) 0x409cf8 EOR X11, X11, X12 |
(57) 0x409cfc STR X11, [X10, #16] |
(57) 0x409d00 B.NE 409ccc |
(49) 0x409d04 SUB W8, W21, #1 |
(49) 0x409d08 MOVZ W11, #396 |
(49) 0x409d0c ORR X9, XZR, XZR |
(49) 0x409d10 PTRUE P1.D, ALL |
(49) 0x409d14 AND X10, X8, X11 |
(49) 0x409d18 EOR X8, X10, X11 |
(49) 0x409d1c MOVZ W11, #623 |
(49) 0x409d20 SUB X11, X11, X10 |
(55) 0x409d24 ADD X12, X28, X9,LSL #3 |
(55) 0x409d28 ADD X9, X9, X21 |
(55) 0x409d2c LD1D {Z0.D}, P1/Z, [X12, X27,LSL #3] |
(55) 0x409d30 LD1D {Z1.D}, P1/Z, [X12, X13,LSL #3] |
(55) 0x409d34 MOVPRFX Z2, Z1 |
(55) 0x409d38 AND Z2.D, Z2.D, #2147483646 |
(55) 0x409d3c AND Z0.D, Z0.D, #-2147483648 |
(55) 0x409d40 AND Z1.D, Z1.D, #1 |
(55) 0x409d44 ORR Z0.D, Z2.D, Z0.D |
(55) 0x409d48 LD1D {Z2.D}, P1/Z, [X12, X24,LSL #3] |
(55) 0x409d4c LSR Z0.D, Z0.D, #63 |
(55) 0x409d50 CMPEQ P0.D, P1/Z, Z1.D, #0 |
(55) 0x409d54 DUP Z1.D, X20 |
(55) 0x409d58 CMP X8, X9 |
(55) 0x409d5c CPY Z1.D, P0/M, #0 |
(55) 0x409d60 EOR Z0.D, Z0.D, Z2.D |
(55) 0x409d64 EOR Z0.D, Z0.D, Z1.D |
(55) 0x409d68 ST1D {Z0.D}, P1, [X12, X27,LSL #3] |
(55) 0x409d6c B.NE 409d24 |
(49) 0x409d70 CBZ X10, 409db8 |
(49) 0x409d74 LDR X9, [SP, #136] |
(49) 0x409d78 LDR X9, [X9, X11,LSL #3] |
(49) 0x409d7c HINT #0 |
(56) 0x409d80 ADD X10, X28, X8,LSL #3 |
(56) 0x409d84 AND X11, X9, #6177 |
(56) 0x409d88 ADD X8, X8, #1 |
(56) 0x409d8c CMP X8, #396 |
(56) 0x409d90 LDR X9, [X10, #1840] |
(56) 0x409d94 AND X12, X9, #6015 |
(56) 0x409d98 ORR X11, X12, X11 |
(56) 0x409d9c LDR X12, [X10, #16] |
(56) 0x409da0 EOR X11, X12, X11,LSR #1 |
(56) 0x409da4 SBFM X12, X9, #0, #0 |
(56) 0x409da8 AND X12, X12, X20 |
(56) 0x409dac EOR X11, X11, X12 |
(56) 0x409db0 STR X11, [X10, #1832] |
(56) 0x409db4 B.NE 409d80 |
(49) 0x409db8 LDR X8, [SP, #136] |
(49) 0x409dbc MOVZ W9, #1 |
(49) 0x409dc0 LDR X10, [X8] |
(49) 0x409dc4 ORR X8, XZR, X10 |
(49) 0x409dc8 B 409fa4 |
(49) 0x409dcc LDR X8, [SP, #136] |
(49) 0x409dd0 ADD X9, X22, #1 |
(49) 0x409dd4 CMP X22, #623 |
(49) 0x409dd8 STR X9, [X28, #5008] |
(49) 0x409ddc LDR X8, [X8, X22,LSL #3] |
(49) 0x409de0 B.NE 409fcc |
(49) 0x409de4 SUB W9, W25, #1 |
(49) 0x409de8 MOVZ W12, #227 |
(49) 0x409dec ORR X10, XZR, XZR |
(49) 0x409df0 PTRUE P2.D, ALL |
(49) 0x409df4 AND X11, X9, X12 |
(49) 0x409df8 EOR X9, X11, X12 |
(49) 0x409dfc ADDVL X12, X28, #1 |
(50) 0x409e00 UBFM X13, X10, #61, #60 |
(50) 0x409e04 ADD X10, X10, X25 |
(50) 0x409e08 ADD X14, X28, X13 |
(50) 0x409e0c ADD X13, X12, X13 |
(50) 0x409e10 LD1D {Z0.D}, P2/Z, [X14, X24,LSL #3] |
(50) 0x409e14 LD1D {Z1.D}, P2/Z, [X13, X24,LSL #3] |
(50) 0x409e18 LD1D {Z3.D}, P2/Z, [X13, X23,LSL #3] |
(50) 0x409e1c LD1D {Z2.D}, P2/Z, [X14, X23,LSL #3] |
(50) 0x409e20 MOVPRFX Z4, Z2 |
(50) 0x409e24 AND Z4.D, Z4.D, #2147483646 |
(50) 0x409e28 MOVPRFX Z5, Z3 |
(50) 0x409e2c AND Z5.D, Z5.D, #2147483646 |
(50) 0x409e30 AND Z0.D, Z0.D, #-2147483648 |
(50) 0x409e34 AND Z1.D, Z1.D, #-2147483648 |
(50) 0x409e38 AND Z3.D, Z3.D, #1 |
(50) 0x409e3c AND Z2.D, Z2.D, #1 |
(50) 0x409e40 ORR Z0.D, Z4.D, Z0.D |
(50) 0x409e44 ORR Z1.D, Z5.D, Z1.D |
(50) 0x409e48 LD1D {Z4.D}, P2/Z, [X14, X19,LSL #3] |
(50) 0x409e4c LD1D {Z5.D}, P2/Z, [X13, X19,LSL #3] |
(50) 0x409e50 CMPEQ P1.D, P2/Z, Z3.D, #0 |
(50) 0x409e54 CMPEQ P0.D, P2/Z, Z2.D, #0 |
(50) 0x409e58 DUP Z2.D, X20 |
(50) 0x409e5c MOVPRFX Z3, Z2 |
(50) 0x409e60 CPY Z3.D, P0/M, #0 |
(50) 0x409e64 CMP X9, X10 |
(50) 0x409e68 LSR Z0.D, Z0.D, #63 |
(50) 0x409e6c LSR Z1.D, Z1.D, #63 |
(50) 0x409e70 CPY Z2.D, P1/M, #0 |
(50) 0x409e74 EOR Z0.D, Z0.D, Z4.D |
(50) 0x409e78 EOR Z1.D, Z1.D, Z5.D |
(50) 0x409e7c EOR Z0.D, Z0.D, Z3.D |
(50) 0x409e80 EOR Z1.D, Z1.D, Z2.D |
(50) 0x409e84 ST1D {Z0.D}, P2, [X14, X24,LSL #3] |
(50) 0x409e88 ST1D {Z1.D}, P2, [X13, X24,LSL #3] |
(50) 0x409e8c B.NE 409e00 |
(49) 0x409e90 MOVZ X14, #230 |
(49) 0x409e94 CBZ X11, 409ed8 |
(49) 0x409e98 LDR X10, [SP, #136] |
(49) 0x409e9c LDR X10, [X10, X9,LSL #3] |
(53) 0x409ea0 ADD X11, X28, X9,LSL #3 |
(53) 0x409ea4 AND X12, X10, #6177 |
(53) 0x409ea8 ADD X9, X9, #1 |
(53) 0x409eac CMP X9, #227 |
(53) 0x409eb0 LDR X10, [X11, #24] |
(53) 0x409eb4 AND X13, X10, #6015 |
(53) 0x409eb8 ORR X12, X13, X12 |
(53) 0x409ebc LDR X13, [X11, #3192] |
(53) 0x409ec0 EOR X12, X13, X12,LSR #1 |
(53) 0x409ec4 SBFM X13, X10, #0, #0 |
(53) 0x409ec8 AND X13, X13, X20 |
(53) 0x409ecc EOR X12, X12, X13 |
(53) 0x409ed0 STR X12, [X11, #16] |
(53) 0x409ed4 B.NE 409ea0 |
(49) 0x409ed8 SUB W9, W21, #1 |
(49) 0x409edc MOVZ W12, #396 |
(49) 0x409ee0 ORR X10, XZR, XZR |
(49) 0x409ee4 PTRUE P1.D, ALL |
(49) 0x409ee8 AND X11, X9, X12 |
(49) 0x409eec EOR X9, X11, X12 |
(49) 0x409ef0 MOVZ W12, #623 |
(49) 0x409ef4 SUB X12, X12, X11 |
(49) 0x409ef8 HINT #0 |
(49) 0x409efc HINT #0 |
(51) 0x409f00 ADD X13, X28, X10,LSL #3 |
(51) 0x409f04 ADD X10, X10, X21 |
(51) 0x409f08 LD1D {Z0.D}, P1/Z, [X13, X27,LSL #3] |
(51) 0x409f0c LD1D {Z1.D}, P1/Z, [X13, X14,LSL #3] |
(51) 0x409f10 MOVPRFX Z2, Z1 |
(51) 0x409f14 AND Z2.D, Z2.D, #2147483646 |
(51) 0x409f18 AND Z0.D, Z0.D, #-2147483648 |
(51) 0x409f1c AND Z1.D, Z1.D, #1 |
(51) 0x409f20 ORR Z0.D, Z2.D, Z0.D |
(51) 0x409f24 LD1D {Z2.D}, P1/Z, [X13, X24,LSL #3] |
(51) 0x409f28 LSR Z0.D, Z0.D, #63 |
(51) 0x409f2c CMPEQ P0.D, P1/Z, Z1.D, #0 |
(51) 0x409f30 DUP Z1.D, X20 |
(51) 0x409f34 CMP X9, X10 |
(51) 0x409f38 CPY Z1.D, P0/M, #0 |
(51) 0x409f3c EOR Z0.D, Z0.D, Z2.D |
(51) 0x409f40 EOR Z0.D, Z0.D, Z1.D |
(51) 0x409f44 ST1D {Z0.D}, P1, [X13, X27,LSL #3] |
(51) 0x409f48 B.NE 409f00 |
(49) 0x409f4c CBZ X11, 409f98 |
(49) 0x409f50 LDR X10, [SP, #136] |
(49) 0x409f54 LDR X10, [X10, X12,LSL #3] |
(49) 0x409f58 HINT #0 |
(49) 0x409f5c HINT #0 |
(52) 0x409f60 ADD X11, X28, X9,LSL #3 |
(52) 0x409f64 AND X12, X10, #6177 |
(52) 0x409f68 ADD X9, X9, #1 |
(52) 0x409f6c CMP X9, #396 |
(52) 0x409f70 LDR X10, [X11, #1840] |
(52) 0x409f74 AND X13, X10, #6015 |
(52) 0x409f78 ORR X12, X13, X12 |
(52) 0x409f7c LDR X13, [X11, #16] |
(52) 0x409f80 EOR X12, X13, X12,LSR #1 |
(52) 0x409f84 SBFM X13, X10, #0, #0 |
(52) 0x409f88 AND X13, X13, X20 |
(52) 0x409f8c EOR X12, X12, X13 |
(52) 0x409f90 STR X12, [X11, #1832] |
(52) 0x409f94 B.NE 409f60 |
(49) 0x409f98 LDR X10, [SP, #136] |
(49) 0x409f9c ORR X9, XZR, XZR |
(49) 0x409fa0 LDR X10, [X10] |
(49) 0x409fa4 LDR X11, [X28, #5000] |
(49) 0x409fa8 AND X12, X10, #6015 |
(49) 0x409fac SBFM X10, X10, #0, #0 |
(49) 0x409fb0 AND X10, X10, X20 |
(49) 0x409fb4 AND X11, X11, #6177 |
(49) 0x409fb8 ORR X11, X12, X11 |
(49) 0x409fbc LDR X12, [X28, #3184] |
(49) 0x409fc0 EOR X11, X12, X11,LSR #1 |
(49) 0x409fc4 EOR X10, X11, X10 |
(49) 0x409fc8 STR X10, [X28, #5000] |
(49) 0x409fcc LDR X10, [SP, #136] |
(49) 0x409fd0 ADD X22, X9, #1 |
(49) 0x409fd4 MOVZ W11, #22144 |
(49) 0x409fd8 MOVZ W12, #61382 |
(49) 0x409fdc STR X22, [X28, #5008] |
(49) 0x409fe0 MOVK W11, #40236 |
(49) 0x409fe4 LDR X9, [X10, X9,LSL #3] |
(49) 0x409fe8 UBFM X10, X9, #11, #42 |
(49) 0x409fec EOR X9, X10, X9 |
(49) 0x409ff0 UBFM W10, W9, #25, #24 |
(49) 0x409ff4 AND X10, X10, X11 |
(49) 0x409ff8 EOR X9, X10, X9 |
(49) 0x409ffc UBFM W10, W9, #17, #16 |
(49) 0x40a000 AND X10, X10, X12 |
(49) 0x40a004 EOR X9, X10, X9 |
(49) 0x40a008 UBFM X10, X8, #11, #42 |
(49) 0x40a00c EOR X8, X10, X8 |
(49) 0x40a010 EOR X9, X9, X9,LSR #18 |
(49) 0x40a014 UBFM W10, W8, #25, #24 |
(49) 0x40a018 AND X10, X10, X11 |
(49) 0x40a01c UCVTF D1, X9 |
(49) 0x40a020 EOR X8, X10, X8 |
(49) 0x40a024 UBFM W10, W8, #17, #16 |
(49) 0x40a028 AND X10, X10, X12 |
(49) 0x40a02c EOR X8, X10, X8 |
(49) 0x40a030 EOR X8, X8, X8,LSR #18 |
(49) 0x40a034 UCVTF D0, X8 |
(49) 0x40a038 MOVZ X8, #16880 |
(49) 0x40a03c FMOV D2, X8 |
(49) 0x40a040 MOVZ X8, #15344 |
(49) 0x40a044 FMADD D0, D1, D2, D0 |
(49) 0x40a048 FMOV D1, X8 |
(49) 0x40a04c FMUL D0, D0, D1 |
(49) 0x40a050 FCMP D0, D8 |
(49) 0x40a054 B.GE 40a070 |
(49) 0x40a058 FMADD D0, D10, D0, D9 |
(49) 0x40a05c STR D0, [X16, X26,LSL #3] |
(49) 0x40a060 ADD X26, X26, #1 |
(49) 0x40a064 CMP X26, X15 |
(49) 0x40a068 B.NE 409c08 |
(46) 0x40a06c B 40a0a0 |
(49) 0x40a070 FMOV D0, #1.0000000 |
(49) 0x40a074 MOVI D1, #0 |
(49) 0x40a078 STP X16, X15, [SP, #16] |
(49) 0x40a07c BL 404bc0 |
(49) 0x40a080 LDP X16, X15, [SP, #16] |
(49) 0x40a084 FMADD D0, D10, D0, D9 |
(49) 0x40a088 STR D0, [X16, X26,LSL #3] |
(49) 0x40a08c ADD X26, X26, #1 |
(49) 0x40a090 CMP X26, X15 |
(49) 0x40a094 B.NE 409c08 |
(46) 0x40a098 HINT #0 |
(46) 0x40a09c HINT #0 |
(46) 0x40a0a0 LDR X26, [SP, #96] |
(46) 0x40a0a4 LDR X8, [SP, #80] |
(46) 0x40a0a8 LDR W2, [X8] |
(46) 0x40a0ac ORR X0, XZR, X28 |
(46) 0x40a0b0 ORR X1, XZR, X26 |
(46) 0x40a0b4 BL 40c7a0 |
(46) 0x40a0b8 LDR X8, [SP, #120] |
(46) 0x40a0bc LDR W8, [X8] |
(46) 0x40a0c0 CMP W8, #1 |
(46) 0x40a0c4 B.LT 40a204 |
(47) 0x40a0c8 ORR X22, XZR, XZR |
(47) 0x40a0cc B 40a0f8 |
0x40a0d0 HINT #0 |
0x40a0d4 HINT #0 |
0x40a0d8 HINT #0 |
0x40a0dc HINT #0 |
(48) 0x40a0e0 LDR X8, [SP, #120] |
(48) 0x40a0e4 ADD X22, X22, #1 |
(48) 0x40a0e8 ADD X26, X26, #24 |
(48) 0x40a0ec LDRSW X8, [X8] |
(48) 0x40a0f0 CMP X22, X8 |
(48) 0x40a0f4 B.GE 40a200 |
(48) 0x40a0f8 LDR X8, [SP, #152] |
(48) 0x40a0fc LDR X8, [X8] |
(48) 0x40a100 LDR X0, [X8, #40] |
(48) 0x40a104 BL 46c6e0 |
(48) 0x40a108 LDR X0, [SP, #128] |
(48) 0x40a10c LDR X1, [SP, #144] |
(48) 0x40a110 ORR W2, WZR, W22 |
(48) 0x40a114 BL 40df00 |
(48) 0x40a118 LDR X8, [SP, #152] |
(48) 0x40a11c LDR X8, [X8] |
(48) 0x40a120 LDR X0, [X8, #40] |
(48) 0x40a124 BL 46c800 |
(48) 0x40a128 LDR X0, [SP, #144] |
(48) 0x40a12c ORR W1, WZR, W22 |
(48) 0x40a130 ORR X2, XZR, X26 |
(48) 0x40a134 MOVZ W3, #1 |
(48) 0x40a138 BL 44a4e0 |
(48) 0x40a13c LDR X8, [SP, #152] |
(48) 0x40a140 LDR X8, [X8] |
(48) 0x40a144 LDR X0, [X8, #48] |
(48) 0x40a148 BL 46c6e0 |
(48) 0x40a14c STP XZR, XZR, [X29, #880] |
(48) 0x40a150 STUR XZR, [X29, #384] |
(48) 0x40a154 LDR X0, [SP, #128] |
(48) 0x40a158 LDR X1, [SP, #144] |
(48) 0x40a15c ORR W2, WZR, W22 |
(48) 0x40a160 SUB X3, X29, #144 |
(48) 0x40a164 BL 40e010 |
(48) 0x40a168 LDR X8, [SP, #152] |
(48) 0x40a16c LDR X8, [X8] |
(48) 0x40a170 LDR X0, [X8, #48] |
(48) 0x40a174 BL 46c800 |
(48) 0x40a178 LDUR X8, [X29, #392] |
(48) 0x40a17c LDR D0, [X8, X22,LSL #3] |
(48) 0x40a180 LDR X8, [SP, #112] |
(48) 0x40a184 LDR D1, [X8] |
(48) 0x40a188 FCMP D0, D1 |
(48) 0x40a18c B.GE 40a1e0 |
(48) 0x40a190 LDR X8, [SP, #152] |
(48) 0x40a194 LDR X8, [X8] |
(48) 0x40a198 LDR X0, [X8, #56] |
(48) 0x40a19c BL 46c6e0 |
(48) 0x40a1a0 LDR X0, [SP, #128] |
(48) 0x40a1a4 LDR X1, [SP, #144] |
(48) 0x40a1a8 ORR W2, WZR, W22 |
(48) 0x40a1ac BL 40e1f0 |
(48) 0x40a1b0 LDR X8, [SP, #152] |
(48) 0x40a1b4 LDR X8, [X8] |
(48) 0x40a1b8 LDR X0, [X8, #56] |
(48) 0x40a1bc BL 46c800 |
(48) 0x40a1c0 LDR X0, [SP, #144] |
(48) 0x40a1c4 ORR W1, WZR, W22 |
(48) 0x40a1c8 BL 44acb0 |
(48) 0x40a1cc LDUR W8, [X29, #460] |
(48) 0x40a1d0 ADD W8, W8, #1 |
(48) 0x40a1d4 STUR W8, [X29, #460] |
(48) 0x40a1d8 B 40a0e0 |
0x40a1dc HINT #0 |
(48) 0x40a1e0 LDR X0, [SP, #144] |
(48) 0x40a1e4 ORR W1, WZR, W22 |
(48) 0x40a1e8 BL 44afd0 |
(48) 0x40a1ec LDR X0, [SP, #128] |
(48) 0x40a1f0 ORR W1, WZR, W22 |
(48) 0x40a1f4 BL 40e330 |
(48) 0x40a1f8 B 40a0e0 |
0x40a1fc HINT #0 |
(47) 0x40a200 LDR X26, [SP, #96] |
(46) 0x40a204 LDR X0, [SP, #128] |
(46) 0x40a208 BL 40e2c0 |
(46) 0x40a20c LDR X8, [SP, #88] |
(46) 0x40a210 LDR W9, [SP, #108] |
(46) 0x40a214 LDR W8, [X8] |
(46) 0x40a218 ADD W9, W9, #1 |
(46) 0x40a21c STR W9, [SP, #108] |
(46) 0x40a220 CMP W9, W8 |
(46) 0x40a224 B.LT 409be0 |
(58) 0x40a228 LDR X0, [SP, #144] |
(58) 0x40a22c ORR W1, WZR, WZR |
(58) 0x40a230 BL 44afe0 |
(58) 0x40a234 LDR X0, [SP, #128] |
(58) 0x40a238 LDR X1, [SP, #144] |
(58) 0x40a23c BL 40e340 |
(58) 0x40a240 LDR X8, [SP, #152] |
(58) 0x40a244 LDR X8, [X8] |
(58) 0x40a248 LDR X0, [X8, #16] |
(58) 0x40a24c BL 46c800 |
(58) 0x40a250 MOVZ W8, #5184 |
(58) 0x40a254 SUB X1, X29, #96 |
(58) 0x40a258 ADD X22, X28, X8 |
(58) 0x40a25c ORR X0, XZR, X22 |
(58) 0x40a260 BL 40b060 |
(58) 0x40a264 LDR X8, [SP, #152] |
(58) 0x40a268 LDR X8, [X8] |
(58) 0x40a26c LDR X26, [X8, #24] |
(58) 0x40a270 ORR X0, XZR, X26 |
(58) 0x40a274 BL 46c6e0 |
(58) 0x40a278 LDR X1, [SP, #144] |
(58) 0x40a27c LDR X2, [SP, #128] |
(58) 0x40a280 ORR X0, XZR, X22 |
(58) 0x40a284 BL 40b2e0 |
(58) 0x40a288 ORR X0, XZR, X26 |
(58) 0x40a28c BL 46c800 |
(58) 0x40a290 LDUR X0, [X29, #392] |
(58) 0x40a294 LDR X22, [SP, #72] |
(58) 0x40a298 CBZ X0, 40a2ac |
(58) 0x40a29c LDUR X8, [X29, #408] |
(58) 0x40a2a0 CMP X8, X0 |
(58) 0x40a2a4 B.EQ 40a394 |
(58) 0x40a2a8 BL 404d90 |
(58) 0x40a2ac ADRP X8, |
(58) 0x40a2b0 ADD X8, X8, #3160 |
(58) 0x40a2b4 STUR X8, [X29, #416] |
(58) 0x40a2b8 LDUR X8, [X29, #432] |
(58) 0x40a2bc CBZ X8, 40a2c8 |
(58) 0x40a2c0 LDUR X0, [X29, #440] |
(58) 0x40a2c4 BL 404a70 |
(58) 0x40a2c8 CBZ W22, 4099a4 |
(58) 0x40a2cc LDR X0, [SP, #96] |
(58) 0x40a2d0 BL 404a70 |
(58) 0x40a2d4 B 4099a4 |
0x40a2d8 LDR W20, [SP, #12] |
0x40a2dc LDR X19, [X29, #112] |
0x40a2e0 ORR W1, WZR, W20 |
0x40a2e4 ADRP X0, |
0x40a2e8 ADD X0, X0, #2928 |
0x40a2ec BL 404cb0 |
0x40a2f0 SUB X8, X29, #52 |
0x40a2f4 ADRP X6, |
0x40a2f8 ORR W1, WZR, W20 |
0x40a2fc ADRP X0, |
0x40a300 ADD X0, X0, #2952 |
0x40a304 STUR X8, [X29, #416] |
0x40a308 ADRP X5, |
0x40a30c ADD X5, X5, #2192 |
0x40a310 SUB X4, X29, #96 |
0x40a314 LDR X6, [X6, #3904] |
0x40a318 MOVZ W2, #1 |
0x40a31c MOVZ W3, #8 |
0x40a320 BL 404c00 |
0x40a324 CMP W0, #2 |
0x40a328 B.EQ 40a360 |
0x40a32c CMP W0, #1 |
0x40a330 B.NE 40a368 |
0x40a334 LDR W8, [X19] |
0x40a338 LDUR W9, [X29, #460] |
0x40a33c ADRP X2, |
0x40a340 ORR W1, WZR, W20 |
0x40a344 ADRP X0, |
0x40a348 ADD X0, X0, #2952 |
0x40a34c ADD W8, W9, W8 |
0x40a350 STR W8, [X19] |
0x40a354 LDR X2, [X2, #3904] |
0x40a358 BL 404920 |
0x40a35c B 40a368 |
0x40a360 LDUR W8, [X29, #460] |
0x40a364 LDADD W8, W8, [X19] |
0x40a368 LDP D9, D8, [SP, #288] |
0x40a36c LDR D10, [SP, #272] |
0x40a370 LDP X20, X19, [SP, #384] |
0x40a374 LDP X22, X21, [SP, #368] |
0x40a378 LDP X24, X23, [SP, #352] |
0x40a37c LDP X26, X25, [SP, #336] |
0x40a380 LDP X28, X27, [SP, #320] |
0x40a384 LDP X29, X30, [SP, #304] |
0x40a388 ADD SP, SP, #400 |
0x40a38c RET |
0x40a390 BL 404d60 |
0x40a394 MOVZ W0, #16 |
0x40a398 BL 404c50 |
0x40a39c ORR X19, XZR, X0 |
0x40a3a0 ADRP X1, |
0x40a3a4 ADD X1, X1, #1385 |
0x40a3a8 BL 4047e0 |
0x40a3ac ADRP X1, |
0x40a3b0 ADRP X2, |
0x40a3b4 ORR X0, XZR, X19 |
0x40a3b8 LDR X1, [X1, #3912] |
0x40a3bc LDR X2, [X2, #3816] |
0x40a3c0 BL 404cc0 |
0x40a3c4 BL 40a4e0 |
0x40a3c8 ORR X20, XZR, X0 |
0x40a3cc ORR X0, XZR, X19 |
0x40a3d0 BL 404be0 |
0x40a3d4 ORR X0, XZR, X20 |
0x40a3d8 BL 40a4e0 |
0x40a3dc BL 40a4e0 |
0x40a3e0 BL 40a4e0 |
0x40a3e4 BL 40a4e0 |
0x40a3e8 BL 40a4e0 |
0x40a3ec BL 40a4e0 |
Coverage (%) | Name | Source Location | Module |
---|
Path / |
Source file and lines | miniqmc.cpp:411-475 |
Module | exec |
nb instructions | 140 |
loop length | 560 |
nb stack references | 0 |
front end | 16.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 11.50 | 11.50 | 19.00 | 19.00 | 19.00 | 19.00 | 1.00 | 1.00 | 0.50 | 0.50 | 15.33 | 15.33 | 15.33 | 11.00 | 11.00 |
cycles | 11.50 | 11.50 | 19.00 | 19.00 | 19.00 | 19.00 | 1.00 | 1.00 | 0.50 | 0.50 | 15.33 | 15.33 | 15.33 | 11.00 | 11.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 16.25 |
Overall L1 | 19.00 |
all | 6% |
load | 33% |
store | 33% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SUB SP, SP, #400 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR D10, [SP, #272] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP D9, D8, [SP, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP X29, X30, [SP, #304] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X28, X27, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X26, X25, [SP, #336] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X24, X23, [SP, #352] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X22, X21, [SP, #368] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, X19, [SP, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #304 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W8, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STR X7, [SP, #88] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X6, [SP, #152] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
SUBS W19, W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
STP X5, X3, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X4, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
B.LT 40a368 <.omp_outlined..64+0xab8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR W20, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X0, <4e78fc> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #2904 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X3, X29, #48 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP W19, WZR, [X29, #488] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STUR XZR, [X29, #460] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
SUB X4, X29, #20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X5, X29, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X6, X29, #44 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STUR W8, [X29, #468] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR W8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR W1, WZR, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 404b00 <@plt_start@+0x510> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDP W8, W10, [X29, #488] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SBFM X10, X10, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP W8, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CSEL W8, W8, W19, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP W10, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
STUR W8, [X29, #488] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
B.GT 40a2dc <.omp_outlined..64+0xa2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X9, [X29, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STR W20, [SP, #12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
MOVZ W20, #45279 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CNTW X25, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
CNTD X21, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
FMOV D8, #1.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
ADD W8, W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ X24, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ X23, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVK W20, #39176 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ X19, #399 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR W8, [SP, #36] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X9, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X9, [X29, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MOVZ X27, #229 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X9, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
SUB X9, X29, #96 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X9, X9, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X9, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ORR X9, XZR, X10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B 4099b8 <.omp_outlined..64+0x108> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
LDR W20, [SP, #12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X19, [X29, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ORR W1, WZR, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X0, <4e72e4> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #2928 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 404cb0 <@plt_start@+0x6c0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB X8, X29, #52 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X6, <4eb2f4> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR W1, WZR, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X0, <4e72fc> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #2952 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STUR X8, [X29, #416] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADRP X5, <200409308> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X5, X5, #2192 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X4, X29, #96 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X6, [X6, #3904] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MOVZ W2, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W3, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 404c00 <@plt_start@+0x610> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP W0, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 40a360 <.omp_outlined..64+0xab0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP W0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.NE 40a368 <.omp_outlined..64+0xab8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR W8, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDUR W9, [X29, #460] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADRP X2, <4eb33c> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR W1, WZR, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X0, <4e7344> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #2952 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W8, W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR W8, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X2, [X2, #3904] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
BL 404920 <@plt_start@+0x330> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
B 40a368 <.omp_outlined..64+0xab8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR W8, [X29, #460] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDADD W8, W8, [X19] | ||||||||||||||||||
LDP D9, D8, [SP, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDR D10, [SP, #272] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDP X20, X19, [SP, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X22, X21, [SP, #368] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X24, X23, [SP, #352] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X26, X25, [SP, #336] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X28, X27, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X29, X30, [SP, #304] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
ADD SP, SP, #400 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
RET | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
BL 404d60 <@plt_start@+0x770> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOVZ W0, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 404c50 <@plt_start@+0x660> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR X19, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X1, <4b43a0> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X1, X1, #1385 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 4047e0 <@plt_start@+0x1f0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADRP X1, <4eb3ac> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X2, <4eb3b0> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X1, [X1, #3912] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X2, [X2, #3816] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
BL 404cc0 <@plt_start@+0x6d0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
BL 40a4e0 <__clang_call_terminate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR X20, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 404be0 <@plt_start@+0x5f0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR X0, XZR, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 40a4e0 <__clang_call_terminate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
BL 40a4e0 <__clang_call_terminate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
BL 40a4e0 <__clang_call_terminate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
BL 40a4e0 <__clang_call_terminate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
BL 40a4e0 <__clang_call_terminate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
BL 40a4e0 <__clang_call_terminate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Source file and lines | miniqmc.cpp:411-475 |
Module | exec |
nb instructions | 140 |
loop length | 560 |
nb stack references | 0 |
front end | 16.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 11.50 | 11.50 | 19.00 | 19.00 | 19.00 | 19.00 | 1.00 | 1.00 | 0.50 | 0.50 | 15.33 | 15.33 | 15.33 | 11.00 | 11.00 |
cycles | 11.50 | 11.50 | 19.00 | 19.00 | 19.00 | 19.00 | 1.00 | 1.00 | 0.50 | 0.50 | 15.33 | 15.33 | 15.33 | 11.00 | 11.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 16.25 |
Overall L1 | 19.00 |
all | 6% |
load | 33% |
store | 33% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SUB SP, SP, #400 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR D10, [SP, #272] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP D9, D8, [SP, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP X29, X30, [SP, #304] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X28, X27, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X26, X25, [SP, #336] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X24, X23, [SP, #352] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X22, X21, [SP, #368] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, X19, [SP, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #304 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W8, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STR X7, [SP, #88] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X6, [SP, #152] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
SUBS W19, W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
STP X5, X3, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X4, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
B.LT 40a368 <.omp_outlined..64+0xab8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR W20, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X0, <4e78fc> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #2904 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X3, X29, #48 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP W19, WZR, [X29, #488] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STUR XZR, [X29, #460] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
SUB X4, X29, #20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X5, X29, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X6, X29, #44 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STUR W8, [X29, #468] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR W8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR W1, WZR, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 404b00 <@plt_start@+0x510> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDP W8, W10, [X29, #488] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SBFM X10, X10, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP W8, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CSEL W8, W8, W19, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP W10, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
STUR W8, [X29, #488] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
B.GT 40a2dc <.omp_outlined..64+0xa2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X9, [X29, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STR W20, [SP, #12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
MOVZ W20, #45279 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CNTW X25, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
CNTD X21, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
FMOV D8, #1.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
ADD W8, W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ X24, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ X23, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVK W20, #39176 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ X19, #399 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR W8, [SP, #36] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X9, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X9, [X29, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MOVZ X27, #229 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X9, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
SUB X9, X29, #96 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X9, X9, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X9, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ORR X9, XZR, X10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B 4099b8 <.omp_outlined..64+0x108> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
LDR W20, [SP, #12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X19, [X29, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ORR W1, WZR, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X0, <4e72e4> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #2928 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 404cb0 <@plt_start@+0x6c0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB X8, X29, #52 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X6, <4eb2f4> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR W1, WZR, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X0, <4e72fc> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #2952 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STUR X8, [X29, #416] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADRP X5, <200409308> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X5, X5, #2192 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X4, X29, #96 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X6, [X6, #3904] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MOVZ W2, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W3, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 404c00 <@plt_start@+0x610> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP W0, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 40a360 <.omp_outlined..64+0xab0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP W0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.NE 40a368 <.omp_outlined..64+0xab8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR W8, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDUR W9, [X29, #460] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADRP X2, <4eb33c> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR W1, WZR, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X0, <4e7344> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #2952 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W8, W9, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR W8, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X2, [X2, #3904] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
BL 404920 <@plt_start@+0x330> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
B 40a368 <.omp_outlined..64+0xab8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR W8, [X29, #460] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDADD W8, W8, [X19] | ||||||||||||||||||
LDP D9, D8, [SP, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDR D10, [SP, #272] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDP X20, X19, [SP, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X22, X21, [SP, #368] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X24, X23, [SP, #352] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X26, X25, [SP, #336] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X28, X27, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X29, X30, [SP, #304] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
ADD SP, SP, #400 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
RET | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
BL 404d60 <@plt_start@+0x770> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOVZ W0, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 404c50 <@plt_start@+0x660> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR X19, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X1, <4b43a0> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X1, X1, #1385 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 4047e0 <@plt_start@+0x1f0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADRP X1, <4eb3ac> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X2, <4eb3b0> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X1, [X1, #3912] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X2, [X2, #3816] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
BL 404cc0 <@plt_start@+0x6d0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
BL 40a4e0 <__clang_call_terminate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR X20, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 404be0 <@plt_start@+0x5f0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR X0, XZR, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 40a4e0 <__clang_call_terminate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
BL 40a4e0 <__clang_call_terminate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
BL 40a4e0 <__clang_call_terminate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
BL 40a4e0 <__clang_call_terminate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
BL 40a4e0 <__clang_call_terminate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
BL 40a4e0 <__clang_call_terminate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼.omp_outlined..64– | 0.01 | 0.02 |
▼Loop 47 - miniqmc.cpp:412-475 - exec– | 0 | 0 |
○Loop 48 - miniqmc.cpp:429-458 - exec | 0.01 | 0.02 |
▼Loop 46 - miniqmc.cpp:412-475 - exec– | 0 | 0 |
▼Loop 49 - StdRandom.h:102-103 - exec– | 0 | 0 |
○Loop 57 - random.tcc:404-409 - exec | 0 | 0 |
○Loop 50 - random.tcc:406-409 - exec | 0 | 0 |
○Loop 55 - random.tcc:414-417 - exec | 0 | 0 |
○Loop 53 - random.tcc:404-409 - exec | 0 | 0 |
○Loop 51 - random.tcc:414-417 - exec | 0 | 0 |
○Loop 56 - random.tcc:412-417 - exec | 0 | 0 |
○Loop 54 - random.tcc:406-409 - exec | 0 | 0 |
○Loop 52 - random.tcc:412-417 - exec | 0 | 0 |
▼Loop 58 - new_allocator.h:120-158 - exec– | 0 | 0 |
○Loop 60 - stl_algobase.h:910-910 - exec | 0 | 0 |
○Loop 61 - stl_algobase.h:910-910 - exec | 0 | 0.01 |
○Loop 59 - alloc_traits.h:261-261 - exec | 0 | 0 |