Loop Id: 316 | Module: exec | Source: BsplineFunctor.h:302-336 | Coverage: 0.01% |
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Loop Id: 316 | Module: exec | Source: BsplineFunctor.h:302-336 | Coverage: 0.01% |
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0x41d880 VMOVSD (%R8,%RDI,8),%XMM2 [2] |
0x41d886 VMOVSD %XMM2,0x40(%RSP) [7] |
0x41d88c VMULSD %XMM2,%XMM3,%XMM2 |
0x41d890 VCVTTSD2SI %XMM2,%R8D |
0x41d894 VROUNDSD $0xb,%XMM2,%XMM2,%XMM3 |
0x41d89a MOVSXD %R8D,%R8 |
0x41d89d VMOVSD (%RSI,%R8,8),%XMM8 [3] |
0x41d8a3 VMOVSD 0x8(%RSI,%R8,8),%XMM6 [3] |
0x41d8aa VMOVSD 0x10(%RSI,%R8,8),%XMM5 [3] |
0x41d8b1 VSUBSD %XMM3,%XMM2,%XMM2 |
0x41d8b5 VMOVSD 0x18(%RSI,%R8,8),%XMM3 [3] |
0x41d8bc VMULSD %XMM2,%XMM2,%XMM7 |
0x41d8c0 VMULSD %XMM2,%XMM7,%XMM4 |
0x41d8c4 VMOVAPD %XMM2,%XMM9 |
0x41d8c8 VFMADD213SD 0x100(%RSP),%XMM1,%XMM9 [7] |
0x41d8d2 VMOVAPD %YMM10,%YMM14 |
0x41d8d7 VMOVAPD %XMM2,%XMM10 |
0x41d8db VMULSD %XMM8,%XMM9,%XMM9 |
0x41d8e0 VMOVUPD 0x190(%RSP),%XMM1 [7] |
0x41d8e9 VFMADD132SD 0xf0(%RSP),%XMM1,%XMM10 [7] |
0x41d8f3 VMOVAPD %XMM2,%XMM11 |
0x41d8f7 VMOVUPD 0x170(%RSP),%XMM1 [7] |
0x41d900 VFMADD132SD 0x180(%RSP),%XMM1,%XMM11 [7] |
0x41d90a VUNPCKLPD %XMM2,%XMM7,%XMM7 |
0x41d90e VFMADD213SD %XMM9,%XMM6,%XMM10 |
0x41d913 VMOVUPD 0x150(%RSP),%XMM1 [7] |
0x41d91c VFMADD132SD 0x160(%RSP),%XMM1,%XMM2 [7] |
0x41d926 VMULPD 0x6a0(%RSP),%XMM7,%XMM9 [7] |
0x41d92f VMOVAPD %XMM0,%XMM1 |
0x41d933 VMOVAPD %XMM15,%XMM0 |
0x41d937 VMOVAPD %YMM13,%YMM15 |
0x41d93c VMOVAPD %XMM12,%XMM13 |
0x41d941 VSHUFPD $0x1,%XMM9,%XMM9,%XMM12 |
0x41d947 VFMADD213SD %XMM10,%XMM5,%XMM11 |
0x41d94c VADDSD %XMM9,%XMM12,%XMM9 |
0x41d951 VADDSD 0x140(%RSP),%XMM9,%XMM9 [7] |
0x41d95a VMULPD 0x680(%RSP),%XMM7,%XMM10 [7] |
0x41d963 VMULSD %XMM8,%XMM9,%XMM9 |
0x41d968 VSHUFPD $0x1,%XMM10,%XMM10,%XMM12 |
0x41d96e VADDSD %XMM10,%XMM12,%XMM10 |
0x41d973 VADDSD 0x130(%RSP),%XMM10,%XMM10 [7] |
0x41d97c VFMADD213SD %XMM11,%XMM3,%XMM2 |
0x41d981 VMULPD 0x1e0(%RSP),%XMM7,%XMM11 [7] |
0x41d98a VSHUFPD $0x1,%XMM11,%XMM11,%XMM12 |
0x41d990 VADDSD %XMM11,%XMM12,%XMM11 |
0x41d995 VFMADD213SD %XMM9,%XMM6,%XMM10 |
0x41d99a VMULPD 0x1c0(%RSP),%XMM7,%XMM9 [7] |
0x41d9a3 VMOVAPD %XMM4,%XMM12 |
0x41d9a7 VFMADD132SD 0xb0(%RSP),%XMM9,%XMM12 [7] |
0x41d9b1 VSHUFPD $0x1,%XMM9,%XMM9,%XMM9 |
0x41d9b7 VADDSD 0xa0(%RSP),%XMM9,%XMM9 [7] |
0x41d9c0 VADDSD %XMM9,%XMM12,%XMM9 |
0x41d9c5 VMOVAPD %XMM13,%XMM12 |
0x41d9ca VMOVAPD %YMM15,%YMM13 |
0x41d9cf VMOVAPD %XMM0,%XMM15 |
0x41d9d3 VMOVAPD %XMM1,%XMM0 |
0x41d9d7 VADDSD 0xd0(%RSP),%XMM11,%XMM11 [7] |
0x41d9e0 VMULSD %XMM8,%XMM9,%XMM8 |
0x41d9e5 VFMADD213SD %XMM10,%XMM5,%XMM11 |
0x41d9ea VMULPD %XMM7,%XMM13,%XMM9 |
0x41d9ee VMOVAPD %XMM4,%XMM10 |
0x41d9f2 VFMADD213SD %XMM9,%XMM12,%XMM10 |
0x41d9f7 VSHUFPD $0x1,%XMM9,%XMM9,%XMM9 |
0x41d9fd VADDSD %XMM15,%XMM9,%XMM9 |
0x41da02 VADDSD %XMM9,%XMM10,%XMM9 |
0x41da07 VMOVAPD %YMM14,%YMM10 |
0x41da0c VMOVUPD 0x90(%RSP),%XMM14 [7] |
0x41da15 VFMADD213SD %XMM8,%XMM6,%XMM9 |
0x41da1a VMULPD %XMM7,%XMM10,%XMM6 |
0x41da1e VMOVAPD %XMM4,%XMM8 |
0x41da22 VFMADD213SD %XMM6,%XMM1,%XMM8 |
0x41da27 VSHUFPD $0x1,%XMM6,%XMM6,%XMM6 |
0x41da2c VADDSD %XMM6,%XMM14,%XMM6 |
0x41da30 VADDSD %XMM6,%XMM8,%XMM6 |
0x41da34 VFMADD213SD %XMM9,%XMM5,%XMM6 |
0x41da39 VMOVUPD 0x1a0(%RSP),%YMM9 [7] |
0x41da42 VMULPD 0x660(%RSP),%XMM7,%XMM5 [7] |
0x41da4b VSHUFPD $0x1,%XMM5,%XMM5,%XMM8 |
0x41da50 VADDSD %XMM5,%XMM8,%XMM5 |
0x41da54 VMOVUPD 0x80(%RSP),%XMM8 [7] |
0x41da5d VADDSD 0xc0(%RSP),%XMM5,%XMM5 [7] |
0x41da66 VFMADD213SD %XMM11,%XMM3,%XMM5 |
0x41da6b VMOVUPD 0x120(%RSP),%XMM11 [7] |
0x41da74 VMULPD %XMM7,%XMM9,%XMM7 |
0x41da78 VFMADD213SD %XMM7,%XMM8,%XMM4 |
0x41da7d VSHUFPD $0x1,%XMM7,%XMM7,%XMM7 |
0x41da82 VADDSD %XMM7,%XMM11,%XMM7 |
0x41da86 VADDSD %XMM7,%XMM4,%XMM4 |
0x41da8a VFMADD213SD %XMM6,%XMM3,%XMM4 |
0x41da8f VMOVUPD 0x110(%RSP),%XMM6 [7] |
0x41da98 VMOVUPD 0xe0(%RSP),%XMM3 [7] |
0x41daa1 MOVSXD (%RAX,%RDI,4),%R8 [8] |
0x41daa5 ADD %R11,%R8 |
0x41daa8 VMULSD %XMM2,%XMM6,%XMM2 |
0x41daac VMOVSD %XMM2,(%RCX,%R8,8) [4] |
0x41dab2 VMULSD %XMM3,%XMM5,%XMM2 |
0x41dab6 VDIVSD 0x40(%RSP),%XMM2,%XMM1 [7] |
0x41dabc VMOVSD %XMM1,(%RDX,%R8,8) [5] |
0x41dac2 VMOVUPD (%RSP),%XMM1 [7] |
0x41dac7 VMOVSD %XMM4,(%R9,%R8,8) [1] |
0x41dacd MOV 0x20(%RBP),%R8 [6] |
0x41dad1 INC %RDI |
0x41dad4 CMP %RDI,%RBX |
0x41dad7 JNE 41d880 |
/home/eoseret/qaas_runs_CPU_9468/171-145-9236/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 302 - 336 |
-------------------------------------------------------------------------------- |
302: #pragma omp simd |
303: for (int j = 0; j < iCount; j++) |
304: { |
305: real_type r = distArrayCompressed[j]; |
306: int iScatter = distIndices[j]; |
307: real_type rinv = cOne / r; |
308: r *= DeltaRInv; |
309: int iGather = (int)r; |
310: real_type t = r - real_type(iGather); |
311: real_type tp0 = t * t * t; |
312: real_type tp1 = t * t; |
313: real_type tp2 = t; |
314: |
315: real_type sCoef0 = SplineCoefs[iGather + 0]; |
316: real_type sCoef1 = SplineCoefs[iGather + 1]; |
317: real_type sCoef2 = SplineCoefs[iGather + 2]; |
318: real_type sCoef3 = SplineCoefs[iGather + 3]; |
319: |
320: // clang-format off |
321: laplArray[iScatter] = dSquareDeltaRinv * |
322: (sCoef0*( d2A[ 2]*tp2 + d2A[ 3])+ |
323: sCoef1*( d2A[ 6]*tp2 + d2A[ 7])+ |
324: sCoef2*( d2A[10]*tp2 + d2A[11])+ |
325: sCoef3*( d2A[14]*tp2 + d2A[15])); |
326: |
327: gradArray[iScatter] = DeltaRInv * rinv * |
328: (sCoef0*( dA[ 1]*tp1 + dA[ 2]*tp2 + dA[ 3])+ |
329: sCoef1*( dA[ 5]*tp1 + dA[ 6]*tp2 + dA[ 7])+ |
330: sCoef2*( dA[ 9]*tp1 + dA[10]*tp2 + dA[11])+ |
331: sCoef3*( dA[13]*tp1 + dA[14]*tp2 + dA[15])); |
332: |
333: valArray[iScatter] = (sCoef0*(A[ 0]*tp0 + A[ 1]*tp1 + A[ 2]*tp2 + A[ 3])+ |
334: sCoef1*(A[ 4]*tp0 + A[ 5]*tp1 + A[ 6]*tp2 + A[ 7])+ |
335: sCoef2*(A[ 8]*tp0 + A[ 9]*tp1 + A[10]*tp2 + A[11])+ |
336: sCoef3*(A[12]*tp0 + A[13]*tp1 + A[14]*tp2 + A[15])); |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 2.40 |
CQA speedup if fully vectorized | 6.90 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.14 |
Bottlenecks | P1, |
Function | _ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi |
Source | BsplineFunctor.h:302-336 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | high |
Unroll/vectorization loop type | peel/tail |
Unroll factor | 1 |
CQA cycles | 25.00 |
CQA cycles if no scalar integer | 25.00 |
CQA cycles if FP arith vectorized | 10.42 |
CQA cycles if fully vectorized | 3.63 |
Front-end cycles | 17.50 |
DIV/SQRT cycles | 22.00 |
P0 cycles | 25.00 |
P1 cycles | 11.00 |
P2 cycles | 11.00 |
P3 cycles | 2.00 |
P4 cycles | 20.50 |
P5 cycles | 1.60 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 1.40 |
P10 cycles | 11.00 |
P11 cycles | 4.00 |
Inter-iter dependencies cycles | 1 - 2 |
FE+BE cycles (UFS) | 26.26 - 26.12 |
Stall cycles (UFS) | 8.05 - 7.95 |
Nb insns | 104.00 |
Nb uops | 105.00 |
Nb loads | 33.00 |
Nb stores | 4.00 |
Nb stack references | 27.00 |
FLOP/cycle | 3.04 |
Nb FLOP add-sub | 17.00 |
Nb FLOP mul | 24.00 |
Nb FLOP fma | 17.00 |
Nb FLOP div | 1.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 17.12 |
Bytes prefetched | 0.00 |
Bytes loaded | 396.00 |
Bytes stored | 32.00 |
Stride 0 | 2.00 |
Stride 1 | 1.00 |
Stride n | 0.00 |
Stride unknown | 5.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 43.30 |
Vectorization ratio load | 48.39 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 50.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 88.89 |
Vector-efficiency ratio all | 19.20 |
Vector-efficiency ratio load | 19.35 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 18.75 |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 27.31 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 2.40 |
CQA speedup if fully vectorized | 6.90 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.14 |
Bottlenecks | P1, |
Function | _ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi |
Source | BsplineFunctor.h:302-336 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | high |
Unroll/vectorization loop type | peel/tail |
Unroll factor | 1 |
CQA cycles | 25.00 |
CQA cycles if no scalar integer | 25.00 |
CQA cycles if FP arith vectorized | 10.42 |
CQA cycles if fully vectorized | 3.63 |
Front-end cycles | 17.50 |
DIV/SQRT cycles | 22.00 |
P0 cycles | 25.00 |
P1 cycles | 11.00 |
P2 cycles | 11.00 |
P3 cycles | 2.00 |
P4 cycles | 20.50 |
P5 cycles | 1.60 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 1.40 |
P10 cycles | 11.00 |
P11 cycles | 4.00 |
Inter-iter dependencies cycles | 1 - 2 |
FE+BE cycles (UFS) | 26.26 - 26.12 |
Stall cycles (UFS) | 8.05 - 7.95 |
Nb insns | 104.00 |
Nb uops | 105.00 |
Nb loads | 33.00 |
Nb stores | 4.00 |
Nb stack references | 27.00 |
FLOP/cycle | 3.04 |
Nb FLOP add-sub | 17.00 |
Nb FLOP mul | 24.00 |
Nb FLOP fma | 17.00 |
Nb FLOP div | 1.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 17.12 |
Bytes prefetched | 0.00 |
Bytes loaded | 396.00 |
Bytes stored | 32.00 |
Stride 0 | 2.00 |
Stride 1 | 1.00 |
Stride n | 0.00 |
Stride unknown | 5.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 43.30 |
Vectorization ratio load | 48.39 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 50.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 88.89 |
Vector-efficiency ratio all | 19.20 |
Vector-efficiency ratio load | 19.35 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 18.75 |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 27.31 |
Path / |
Function | _ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi |
Source file and lines | BsplineFunctor.h:302-336 |
Module | exec |
nb instructions | 104 |
nb uops | 105 |
loop length | 605 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 16 |
used ymm registers | 5 |
used zmm registers | 0 |
nb stack references | 27 |
ADD-SUB / MUL ratio | 1.06 |
micro-operation queue | 17.50 cycles |
front end | 17.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 22.00 | 21.50 | 11.00 | 11.00 | 2.00 | 20.50 | 1.60 | 2.00 | 2.00 | 2.00 | 1.40 | 11.00 |
cycles | 22.00 | 25.00 | 11.00 | 11.00 | 2.00 | 20.50 | 1.60 | 2.00 | 2.00 | 2.00 | 1.40 | 11.00 |
Cycles executing div or sqrt instructions | 4.00 |
Longest recurrence chain latency (RecMII) | 1.00-2.00 |
FE+BE cycles | 26.26-26.12 |
Stall cycles | 8.05-7.95 |
RS full (events) | 18.69-18.79 |
PRF_FLOAT full (events) | 0.32-0.23 |
Front-end | 17.50 |
Dispatch | 25.00 |
DIV/SQRT | 4.00 |
Data deps. | 1.00-2.00 |
Overall L1 | 25.00 |
all | 43% |
load | 48% |
store | 0% |
mul | 50% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 88% |
all | 19% |
load | 19% |
store | 12% |
mul | 18% |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 27% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSD (%R8,%RDI,8),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM2,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD %XMM2,%XMM3,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTTSD2SI %XMM2,%R8D | 2 | 1.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VROUNDSD $0xb,%XMM2,%XMM2,%XMM3 | 2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
MOVSXD %R8D,%R8 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
VMOVSD (%RSI,%R8,8),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x8(%RSI,%R8,8),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x10(%RSI,%R8,8),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBSD %XMM3,%XMM2,%XMM2 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVSD 0x18(%RSI,%R8,8),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMULSD %XMM2,%XMM2,%XMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM2,%XMM7,%XMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVAPD %XMM2,%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VFMADD213SD 0x100(%RSP),%XMM1,%XMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVAPD %YMM10,%YMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %XMM2,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMULSD %XMM8,%XMM9,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD 0x190(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VFMADD132SD 0xf0(%RSP),%XMM1,%XMM10 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVAPD %XMM2,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVUPD 0x170(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VFMADD132SD 0x180(%RSP),%XMM1,%XMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VUNPCKLPD %XMM2,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VFMADD213SD %XMM9,%XMM6,%XMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD 0x150(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VFMADD132SD 0x160(%RSP),%XMM1,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMULPD 0x6a0(%RSP),%XMM7,%XMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVAPD %XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %XMM15,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %YMM13,%YMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %XMM12,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VSHUFPD $0x1,%XMM9,%XMM9,%XMM12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VFMADD213SD %XMM10,%XMM5,%XMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM9,%XMM12,%XMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD 0x140(%RSP),%XMM9,%XMM9 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMULPD 0x680(%RSP),%XMM7,%XMM10 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMULSD %XMM8,%XMM9,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSHUFPD $0x1,%XMM10,%XMM10,%XMM12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM10,%XMM12,%XMM10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD 0x130(%RSP),%XMM10,%XMM10 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VFMADD213SD %XMM11,%XMM3,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD 0x1e0(%RSP),%XMM7,%XMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VSHUFPD $0x1,%XMM11,%XMM11,%XMM12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM11,%XMM12,%XMM11 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD213SD %XMM9,%XMM6,%XMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD 0x1c0(%RSP),%XMM7,%XMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVAPD %XMM4,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VFMADD132SD 0xb0(%RSP),%XMM9,%XMM12 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VSHUFPD $0x1,%XMM9,%XMM9,%XMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD 0xa0(%RSP),%XMM9,%XMM9 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VADDSD %XMM9,%XMM12,%XMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVAPD %XMM13,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %YMM15,%YMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %XMM0,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VADDSD 0xd0(%RSP),%XMM11,%XMM11 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMULSD %XMM8,%XMM9,%XMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SD %XMM10,%XMM5,%XMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %XMM7,%XMM13,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVAPD %XMM4,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VFMADD213SD %XMM9,%XMM12,%XMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSHUFPD $0x1,%XMM9,%XMM9,%XMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM15,%XMM9,%XMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM9,%XMM10,%XMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVAPD %YMM14,%YMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVUPD 0x90(%RSP),%XMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VFMADD213SD %XMM8,%XMM6,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %XMM7,%XMM10,%XMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVAPD %XMM4,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VFMADD213SD %XMM6,%XMM1,%XMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSHUFPD $0x1,%XMM6,%XMM6,%XMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM6,%XMM14,%XMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM6,%XMM8,%XMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD213SD %XMM9,%XMM5,%XMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD 0x1a0(%RSP),%YMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMULPD 0x660(%RSP),%XMM7,%XMM5 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VSHUFPD $0x1,%XMM5,%XMM5,%XMM8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM5,%XMM8,%XMM5 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPD 0x80(%RSP),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VADDSD 0xc0(%RSP),%XMM5,%XMM5 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VFMADD213SD %XMM11,%XMM3,%XMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD 0x120(%RSP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMULPD %XMM7,%XMM9,%XMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SD %XMM7,%XMM8,%XMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSHUFPD $0x1,%XMM7,%XMM7,%XMM7 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM7,%XMM11,%XMM7 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM7,%XMM4,%XMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD213SD %XMM6,%XMM3,%XMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD 0x110(%RSP),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0xe0(%RSP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
MOVSXD (%RAX,%RDI,4),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R11,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMULSD %XMM2,%XMM6,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM2,(%RCX,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD %XMM3,%XMM5,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVSD 0x40(%RSP),%XMM2,%XMM1 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 4 |
VMOVSD %XMM1,(%RDX,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVUPD (%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVSD %XMM4,(%R9,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RDI,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 41d880 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x9a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | _ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi |
Source file and lines | BsplineFunctor.h:302-336 |
Module | exec |
nb instructions | 104 |
nb uops | 105 |
loop length | 605 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 16 |
used ymm registers | 5 |
used zmm registers | 0 |
nb stack references | 27 |
ADD-SUB / MUL ratio | 1.06 |
micro-operation queue | 17.50 cycles |
front end | 17.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 22.00 | 21.50 | 11.00 | 11.00 | 2.00 | 20.50 | 1.60 | 2.00 | 2.00 | 2.00 | 1.40 | 11.00 |
cycles | 22.00 | 25.00 | 11.00 | 11.00 | 2.00 | 20.50 | 1.60 | 2.00 | 2.00 | 2.00 | 1.40 | 11.00 |
Cycles executing div or sqrt instructions | 4.00 |
Longest recurrence chain latency (RecMII) | 1.00-2.00 |
FE+BE cycles | 26.26-26.12 |
Stall cycles | 8.05-7.95 |
RS full (events) | 18.69-18.79 |
PRF_FLOAT full (events) | 0.32-0.23 |
Front-end | 17.50 |
Dispatch | 25.00 |
DIV/SQRT | 4.00 |
Data deps. | 1.00-2.00 |
Overall L1 | 25.00 |
all | 43% |
load | 48% |
store | 0% |
mul | 50% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 88% |
all | 19% |
load | 19% |
store | 12% |
mul | 18% |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 27% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSD (%R8,%RDI,8),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM2,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD %XMM2,%XMM3,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTTSD2SI %XMM2,%R8D | 2 | 1.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VROUNDSD $0xb,%XMM2,%XMM2,%XMM3 | 2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
MOVSXD %R8D,%R8 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
VMOVSD (%RSI,%R8,8),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x8(%RSI,%R8,8),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x10(%RSI,%R8,8),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBSD %XMM3,%XMM2,%XMM2 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVSD 0x18(%RSI,%R8,8),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMULSD %XMM2,%XMM2,%XMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM2,%XMM7,%XMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVAPD %XMM2,%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VFMADD213SD 0x100(%RSP),%XMM1,%XMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVAPD %YMM10,%YMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %XMM2,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMULSD %XMM8,%XMM9,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD 0x190(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VFMADD132SD 0xf0(%RSP),%XMM1,%XMM10 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVAPD %XMM2,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVUPD 0x170(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VFMADD132SD 0x180(%RSP),%XMM1,%XMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VUNPCKLPD %XMM2,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VFMADD213SD %XMM9,%XMM6,%XMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD 0x150(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VFMADD132SD 0x160(%RSP),%XMM1,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMULPD 0x6a0(%RSP),%XMM7,%XMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVAPD %XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %XMM15,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %YMM13,%YMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %XMM12,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VSHUFPD $0x1,%XMM9,%XMM9,%XMM12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VFMADD213SD %XMM10,%XMM5,%XMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSD %XMM9,%XMM12,%XMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD 0x140(%RSP),%XMM9,%XMM9 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMULPD 0x680(%RSP),%XMM7,%XMM10 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMULSD %XMM8,%XMM9,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSHUFPD $0x1,%XMM10,%XMM10,%XMM12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM10,%XMM12,%XMM10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD 0x130(%RSP),%XMM10,%XMM10 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VFMADD213SD %XMM11,%XMM3,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD 0x1e0(%RSP),%XMM7,%XMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VSHUFPD $0x1,%XMM11,%XMM11,%XMM12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM11,%XMM12,%XMM11 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD213SD %XMM9,%XMM6,%XMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD 0x1c0(%RSP),%XMM7,%XMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVAPD %XMM4,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VFMADD132SD 0xb0(%RSP),%XMM9,%XMM12 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VSHUFPD $0x1,%XMM9,%XMM9,%XMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD 0xa0(%RSP),%XMM9,%XMM9 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VADDSD %XMM9,%XMM12,%XMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVAPD %XMM13,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %YMM15,%YMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %XMM0,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VADDSD 0xd0(%RSP),%XMM11,%XMM11 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMULSD %XMM8,%XMM9,%XMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SD %XMM10,%XMM5,%XMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %XMM7,%XMM13,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVAPD %XMM4,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VFMADD213SD %XMM9,%XMM12,%XMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSHUFPD $0x1,%XMM9,%XMM9,%XMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM15,%XMM9,%XMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM9,%XMM10,%XMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVAPD %YMM14,%YMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVUPD 0x90(%RSP),%XMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VFMADD213SD %XMM8,%XMM6,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %XMM7,%XMM10,%XMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVAPD %XMM4,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VFMADD213SD %XMM6,%XMM1,%XMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSHUFPD $0x1,%XMM6,%XMM6,%XMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM6,%XMM14,%XMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM6,%XMM8,%XMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD213SD %XMM9,%XMM5,%XMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD 0x1a0(%RSP),%YMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMULPD 0x660(%RSP),%XMM7,%XMM5 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VSHUFPD $0x1,%XMM5,%XMM5,%XMM8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM5,%XMM8,%XMM5 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPD 0x80(%RSP),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VADDSD 0xc0(%RSP),%XMM5,%XMM5 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VFMADD213SD %XMM11,%XMM3,%XMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD 0x120(%RSP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMULPD %XMM7,%XMM9,%XMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SD %XMM7,%XMM8,%XMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSHUFPD $0x1,%XMM7,%XMM7,%XMM7 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM7,%XMM11,%XMM7 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDSD %XMM7,%XMM4,%XMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD213SD %XMM6,%XMM3,%XMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD 0x110(%RSP),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0xe0(%RSP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
MOVSXD (%RAX,%RDI,4),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R11,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMULSD %XMM2,%XMM6,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM2,(%RCX,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD %XMM3,%XMM5,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVSD 0x40(%RSP),%XMM2,%XMM1 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 4 |
VMOVSD %XMM1,(%RDX,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVUPD (%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVSD %XMM4,(%R9,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RDI,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 41d880 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x9a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |