Loop Id: 835 | Module: exec | Source: inner_product.hpp:211-212 | Coverage: 0.13% |
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Loop Id: 835 | Module: exec | Source: inner_product.hpp:211-212 | Coverage: 0.13% |
---|
0x43d6d0 VMOVQ %R9,%XMM5 |
0x43d6d5 VPBROADCASTQ %XMM5,%YMM5 |
0x43d6da VPOR %YMM1,%YMM5,%YMM5 |
0x43d6de VPMULUDQ %YMM5,%YMM2,%YMM6 |
0x43d6e2 VPSRLQ $0x20,%YMM5,%YMM7 |
0x43d6e7 VPMULUDQ %YMM7,%YMM0,%YMM7 |
0x43d6eb VPADDQ %YMM6,%YMM7,%YMM6 |
0x43d6ef VPSLLQ $0x20,%YMM6,%YMM6 |
0x43d6f4 VPMULUDQ %YMM5,%YMM0,%YMM5 |
0x43d6f8 VPADDQ %YMM4,%YMM5,%YMM5 |
0x43d6fc VPADDQ %YMM6,%YMM5,%YMM5 |
0x43d700 VPSLLQ $0x3,%YMM5,%YMM5 |
0x43d705 VPADDQ %YMM5,%YMM3,%YMM5 |
0x43d709 VMOVQ %XMM5,%RCX |
0x43d70e VPEXTRQ $0x1,%XMM5,%RDX |
0x43d714 VEXTRACTI128 $0x1,%YMM5,%XMM5 |
0x43d71a VMOVQ %XMM5,%R10 |
0x43d71f VPEXTRQ $0x1,%XMM5,%R13 |
0x43d725 VMOVSD (%RCX),%XMM5 [2] |
0x43d729 VMOVHPS (%RDX),%XMM5,%XMM5 [5] |
0x43d72d VMOVSD (%R10),%XMM6 [1] |
0x43d732 VMOVHPS (%R13),%XMM6,%XMM6 [3] |
0x43d738 VMOVUPS %XMM6,0x10(%R15,%R9,8) [4] |
0x43d73f VMOVUPS %XMM5,(%R15,%R9,8) [4] |
0x43d745 ADD $0x4,%R9 |
0x43d749 CMP %RSI,%R9 |
0x43d74c JBE 43d6d0 |
/scratch_na/users/xoserete/qaas_runs/171-284-5201/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 211 - 212 |
-------------------------------------------------------------------------------- |
211: for (size_t j = 0; j < m; ++j) |
212: B[i * ldb + j] = A[j * lda + i]; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 3.03 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.57 |
Bottlenecks | P0, P1, P5, |
Function | qmcplusplus::DiracMatrix |
Source | inner_product.hpp:211-212 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 4 |
CQA cycles | 7.33 |
CQA cycles if no scalar integer | 7.33 |
CQA cycles if FP arith vectorized | 7.33 |
CQA cycles if fully vectorized | 2.42 |
Front-end cycles | 4.67 |
DIV/SQRT cycles | 7.33 |
P0 cycles | 7.33 |
P1 cycles | 1.33 |
P2 cycles | 1.33 |
P3 cycles | 1.00 |
P4 cycles | 7.33 |
P5 cycles | 1.00 |
P6 cycles | 1.00 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 0.00 |
P10 cycles | 1.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 8.15 - 8.45 |
Stall cycles (UFS) | 3.03 - 3.29 |
Nb insns | 27.00 |
Nb uops | 28.00 |
Nb loads | 4.00 |
Nb stores | 2.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 8.73 |
Bytes prefetched | 0.00 |
Bytes loaded | 32.00 |
Bytes stored | 32.00 |
Stride 0 | 0.00 |
Stride 1 | 1.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 4.00 |
Vectorization ratio all | 66.67 |
Vectorization ratio load | 50.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 45.45 |
Vector-efficiency ratio all | 31.25 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 25.00 |
Vector-efficiency ratio mul | 50.00 |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 27.27 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 3.03 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.57 |
Bottlenecks | P0, P1, P5, |
Function | qmcplusplus::DiracMatrix |
Source | inner_product.hpp:211-212 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 4 |
CQA cycles | 7.33 |
CQA cycles if no scalar integer | 7.33 |
CQA cycles if FP arith vectorized | 7.33 |
CQA cycles if fully vectorized | 2.42 |
Front-end cycles | 4.67 |
DIV/SQRT cycles | 7.33 |
P0 cycles | 7.33 |
P1 cycles | 1.33 |
P2 cycles | 1.33 |
P3 cycles | 1.00 |
P4 cycles | 7.33 |
P5 cycles | 1.00 |
P6 cycles | 1.00 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 0.00 |
P10 cycles | 1.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 8.15 - 8.45 |
Stall cycles (UFS) | 3.03 - 3.29 |
Nb insns | 27.00 |
Nb uops | 28.00 |
Nb loads | 4.00 |
Nb stores | 2.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 8.73 |
Bytes prefetched | 0.00 |
Bytes loaded | 32.00 |
Bytes stored | 32.00 |
Stride 0 | 0.00 |
Stride 1 | 1.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 4.00 |
Vectorization ratio all | 66.67 |
Vectorization ratio load | 50.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 45.45 |
Vector-efficiency ratio all | 31.25 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 25.00 |
Vector-efficiency ratio mul | 50.00 |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 27.27 |
Path / |
Function | qmcplusplus::DiracMatrix |
Source file and lines | inner_product.hpp:211-212 |
Module | exec |
nb instructions | 27 |
nb uops | 28 |
loop length | 126 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 8 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.67 cycles |
front end | 4.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.33 | 7.33 | 1.33 | 1.33 | 1.00 | 7.33 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 1.33 |
cycles | 7.33 | 7.33 | 1.33 | 1.33 | 1.00 | 7.33 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 1.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 8.15-8.45 |
Stall cycles | 3.03-3.28 |
LM full (events) | 3.67-3.92 |
Front-end | 4.67 |
Dispatch | 7.33 |
Data deps. | 1.00 |
Overall L1 | 7.33 |
all | 66% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 45% |
all | 66% |
load | 50% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 66% |
load | 50% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 45% |
all | 36% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 27% |
all | 16% |
load | 12% |
store | 25% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 31% |
load | 12% |
store | 25% |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 27% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVQ %R9,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPBROADCASTQ %XMM5,%YMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPOR %YMM1,%YMM5,%YMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPMULUDQ %YMM5,%YMM2,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPSRLQ $0x20,%YMM5,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
VPMULUDQ %YMM7,%YMM0,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPADDQ %YMM6,%YMM7,%YMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPSLLQ $0x20,%YMM6,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
VPMULUDQ %YMM5,%YMM0,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPADDQ %YMM4,%YMM5,%YMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPADDQ %YMM6,%YMM5,%YMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPSLLQ $0x3,%YMM5,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
VPADDQ %YMM5,%YMM3,%YMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVQ %XMM5,%RCX | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPEXTRQ $0x1,%XMM5,%RDX | 2 | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 |
VEXTRACTI128 $0x1,%YMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVQ %XMM5,%R10 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPEXTRQ $0x1,%XMM5,%R13 | 2 | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 |
VMOVSD (%RCX),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVHPS (%RDX),%XMM5,%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4-12 | 1 |
VMOVSD (%R10),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVHPS (%R13),%XMM6,%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4-12 | 1 |
VMOVUPS %XMM6,0x10(%R15,%R9,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPS %XMM5,(%R15,%R9,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
ADD $0x4,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RSI,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 43d6d0 <_ZN11qmcplusplus11DiracMatrixIddE16invert_transposeERKNS_6MatrixIdSaIdEEERS4_RdS8_+0x280> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | qmcplusplus::DiracMatrix |
Source file and lines | inner_product.hpp:211-212 |
Module | exec |
nb instructions | 27 |
nb uops | 28 |
loop length | 126 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 8 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.67 cycles |
front end | 4.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.33 | 7.33 | 1.33 | 1.33 | 1.00 | 7.33 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 1.33 |
cycles | 7.33 | 7.33 | 1.33 | 1.33 | 1.00 | 7.33 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 1.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 8.15-8.45 |
Stall cycles | 3.03-3.28 |
LM full (events) | 3.67-3.92 |
Front-end | 4.67 |
Dispatch | 7.33 |
Data deps. | 1.00 |
Overall L1 | 7.33 |
all | 66% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 45% |
all | 66% |
load | 50% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 66% |
load | 50% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 45% |
all | 36% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 27% |
all | 16% |
load | 12% |
store | 25% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 31% |
load | 12% |
store | 25% |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 27% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVQ %R9,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPBROADCASTQ %XMM5,%YMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPOR %YMM1,%YMM5,%YMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPMULUDQ %YMM5,%YMM2,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPSRLQ $0x20,%YMM5,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
VPMULUDQ %YMM7,%YMM0,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPADDQ %YMM6,%YMM7,%YMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPSLLQ $0x20,%YMM6,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
VPMULUDQ %YMM5,%YMM0,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0.50 |
VPADDQ %YMM4,%YMM5,%YMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPADDQ %YMM6,%YMM5,%YMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPSLLQ $0x3,%YMM5,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
VPADDQ %YMM5,%YMM3,%YMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVQ %XMM5,%RCX | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPEXTRQ $0x1,%XMM5,%RDX | 2 | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 |
VEXTRACTI128 $0x1,%YMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVQ %XMM5,%R10 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPEXTRQ $0x1,%XMM5,%R13 | 2 | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 |
VMOVSD (%RCX),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVHPS (%RDX),%XMM5,%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4-12 | 1 |
VMOVSD (%R10),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVHPS (%R13),%XMM6,%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4-12 | 1 |
VMOVUPS %XMM6,0x10(%R15,%R9,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPS %XMM5,(%R15,%R9,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
ADD $0x4,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RSI,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 43d6d0 <_ZN11qmcplusplus11DiracMatrixIddE16invert_transposeERKNS_6MatrixIdSaIdEEERS4_RdS8_+0x280> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |